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Add verible (Verilog + SystemVerilog) code formatter + linter #54

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mithro opened this issue Sep 14, 2020 · 1 comment
Open

Add verible (Verilog + SystemVerilog) code formatter + linter #54

mithro opened this issue Sep 14, 2020 · 1 comment

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@mithro
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mithro commented Sep 14, 2020

Having a HDL code formatter (similar to clang-format) included in the tools would be nice, one such tool is Verible from Google. Seeing how to nicely format HDL code is useful for a beginner :-) -- Verible also does linting.

Verible is already /mostly/ statically linked and provides release on every commit (see https://github.com/google/verible/releases) and the binary is only ~5mb or less.

One problem is that Windows / Mac OS X support is currently lacking (which could be easy to fix by someone who knows about portability?) and it uses Bazel to build (being a Google project).

@edbordin
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Sounds like a great candidate for inclusion. The cross-platform support is probably a sticking point for me though. I've used bazel with tensorflow before and it looked like setting up anything custom was a pretty steep learning curve...

It looks switching on fully_static_link in the features attribute https://docs.bazel.build/versions/master/be/c-cpp.html#cc_binary.linkstatic would be enough to build the linux binaries the same way I've been doing it. I'd probably rather let someone else contribute OS X support, but I can see if I can convince bazel to work building verible with MSYS2/MinGW.

related to #24

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