about.in

@header About@

<h1>About</h1>

<p>Yosys is a framework for Verilog RTL synthesis. It currently has
extensive Verilog-2005 support and provides a basic set of
synthesis algorithms for various application domains. Selected features
and typical applications:</p>

<ul>
<li>Process almost any synthesizable Verilog-2005 design
<li>Converting Verilog to BLIF / EDIF/ BTOR / SMT-LIB / simple RTL Verilog / etc.
<li>Built-in formal methods for checking properties and equivalence
<li>Mapping to ASIC standard cell libraries (in Liberty File Format)
<li>Mapping to Xilinx 7-Series and Lattice iCE40 and ECP5 FPGAs
<li>Foundation and/or front-end for custom flows
</ul>

<p>Yosys can be adapted to perform any synthesis job by combining
the existing passes (algorithms) using synthesis scripts and
adding additional passes as needed by extending the Yosys C++
code base.</p>

<p>Yosys also serves as backend for several tools that use formal methods to
reason about designs, such as <a href="https://yosyshq.readthedocs.io/en/latest/tools.html#formal-assertions-based-verification-abv-with-symbiyosys-sby">sby</a>
for SMT-solver-based formal property checking or <a href="https://yosyshq.readthedocs.io/en/latest/tools.html#mutation-coverage-with-yosys-mcy">mcy</a>
for evaluating the quality of testbenches with mutation coverage metrics.<p>

<p>Yosys is free software licensed under the <a
href="http://en.wikipedia.org/wiki/ISC_license">ISC license</a> (a GPL
compatible license that is similar in terms to the MIT license or the
2-clause BSD license).</p>

<h2>Example Usage</h2>

<p>Yosys is controlled using synthesis scripts. For example, the following
Yosys synthesis script reads a design (with the top module <tt>mytop</tt>) from
the verilog file <tt>mydesign.v</tt>, synthesizes it to a gate-level netlist
using the cell library in the Liberty file <tt>mycells.lib</tt> and writes the
synthesized results as Verilog netlist to <tt>synth.v</tt>:</p>

<pre># read design
read_verilog mydesign.v

# elaborate design hierarchy
hierarchy -check -top mytop

# the high-level stuff
proc; opt; fsm; opt; memory; opt

# mapping to internal cell library
techmap; opt

# mapping flip-flops to mycells.lib
dfflibmap -liberty mycells.lib

# mapping logic to mycells.lib
abc -liberty mycells.lib

# cleanup
clean

# write synthesized design
write_verilog synth.v</pre>

<p>The <tt>synth</tt> command provides a good default script that can be used
as basis for simple synthesis scripts:</p>

<pre># read design
read_verilog mydesign.v

# generic synthesis
synth -top mytop

# mapping to mycells.lib
dfflibmap -liberty mycells.lib
abc -liberty mycells.lib
clean

# write synthesized design
write_verilog synth.v</pre>

<p>See <a href="https://yosys.readthedocs.io/en/latest/cmd/synth.html"><tt>help synth</tt></a> for details on the <tt>synth</tt> command.

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