documentation.in

@header Documentation@

<h1>Documentation</h1>

<p>This page has links to some documentaton resources available for Yosys.</p>

<h2>Yosys Manual</h2>

<p>A quick first-steps tutorial can be found in the <a
href="https://github.com/YosysHQ/yosys/blob/master/README.md#getting-started">README file</a>.</p>

<p>The <a href="https://yosys.readthedocs.io/en/latest/">Yosys manual</a>
contains information about the internals of Yosys, and a detailed guide through
how to use the tool.  Descriptions of all commands available within Yosys are
available through the <a
href="https://yosys.readthedocs.io/en/latest/cmd_ref.html">command reference</a>
in the manual.  Or, download the <a
href="https://yosys.readthedocs.io/_/downloads/en/latest/pdf/">manual
pdf</a>.</p>

<p>The <a href="https://yosyshq.readthedocs.io/en/latest/">YosysHQ ReadTheDocs</a> has links to many resources for Yosys and Yosys-based tools.</p>

<h2>Support</h2>

The best places to ask questions are the <a
href="https://join.slack.com/t/yosyshq/shared_invite/zt-oe2nxfpv-BJd_9CZpkk_MoTT0s88GcA">YosysHQ Community Slack</a>
and <a href="https://web.libera.chat/#yosys">#yosys on Libera Chat</a>.

The best place to report a bug is on <a
href="https://github.com/YosysHQ/yosys/issues/new">GitHub</a>.

<h2>Papers and other Publications</h2>

<p>Yosys is used in many academic projects. Below are a few papers from the
authors of Yosys. If you would like to use Yosys in your research or teaching,
but you need VHDL features not implemented in the open source frontend such as
VHDL or SystemVerilog Assertion support, <a href="https://www.yosyshq.com/contact">contact YosysHQ</a>
for an academic license!</p>

<ul class="list">
<li>C. Wolf, J. Glaser. Yosys - A Free Verilog Synthesis Suite.
In <i>Proceedings of Austrochip 2013</i>.
[<a href="files/yosys-austrochip2013.pdf">download pdf</a>]
<li>J. Glaser and C. Wolf. Methodology and Example-Driven Interconnect
Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable
Architectures. In Jan Haase, editor, <i>Models, Methods, and Tools for
Complex Chip Design. Lecture Notes in Electrical Engineering. Volume 265,
2014, pp 201-221. Springer, 2013.</i>
[<a href="files/intersynth-yosys-springer2013.pdf">download pdf</a>]
<li>D. Shah, E. Hung, C. Wolf, S. Bazanski, D. Gisselquist, and M. Milanovic. Yosys + nextpnr: an Open Source Framework from Verilog to Bitstream for Commercial FPGAs. In <i>2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE, 2019.</i>
[<a href="https://arxiv.org/abs/1903.10407">arXiv</a>]
</ul>

In papers and reports, please refer to Yosys as follows: <b>Claire Wolf.
Yosys Open SYnthesis Suite. https://yosyshq.net/yosys/</b>, e.g. using the
following BibTeX code:

<pre class="small">@MISC{Yosys,
	author = {Claire Wolf},
	title = {Yosys Open SYnthesis Suite},
	howpublished = "\url{https://yosyshq.net/yosys/}"
}</pre>

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