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<a class="nav-link dropdown-toggle" href="#" id="dropdown_hof" data-toggle="dropdown" aria-haspopup="true" aria-expanded="false"><i class="fa fa-list" aria-hidden="true"> </i>Software Decoders Hall of Fame </a>
<div class="dropdown-menu dropdown-menu-right" aria-labelledby="dropdown_hof">
<h6 class="dropdown-header">Synoptic tables</h6>
<a class="dropdown-item" href="hof_turbo.html">Turbo Codes</a>
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<h1 class="display-4">FEC Software Decoders Hall of Fame</h1>
<p class="lead">This page presents <b>a Channel Coding Software Decoders "Hall of Fame"</b>. It allows to see at a glance what has been achieved, what can be expected from today software decoders, and easily compare their respective characteristics. For now, three wide code families are considered: <b>the Turbo codes (LTE, LTE-Advanced, CCSDS, etc.), the Low-Density Parity-Check (LDPC) codes (5G, Wi-Fi, WiMAX, CCSDS, WRAN, DVB-S2, etc.), and the more recently introduced Polar codes (5G)</b>.</p>
<p class="lead">All the presented results, collected from the state-of-the-art research papers published in the field, consider a <b>BPSK (Bit Phase-Shift Keying) modulation/demodulation</b> and an <b>AWGN (Additive White Gaussian Noise) channel</b>.</p>
<p class="lead"><b>This Hall of Fame strives to present results as fairly as possible</b>: for example, early termination criteria are not taken into consideration while computing throughput, in order to compare raw performances using a consistent method. It remains possible, however, for typos/glitches/mistakes to have inadvertantly made it to the scoreboard. In that eventuality, do not hesitate to contact us. If you would like to have your decoder listed as well in the Hall of Fame: <b>please send us the corresponding research paper references, and we will be delighted to add them</b>.</p>
<p class="lead">In <span class="bg-info text-white">blue</span>, the results simulated or reproducible with <a href="index.html">AFF3CT</a>: our Open-source communication chain dedicated to the Forward Error Correction (FEC) simulations.</p>
<p class="lead text-right">
<i>Last update: 2021-05-17.</i>
</p>
<hr>
<p>Do you like the FEC Software Decoders Hall of Fame? Is it useful in your research works? If yes, you can thank us by citing the following journal article: <strong>A. Cassagne et al., “<a href="https://doi.org/10.1016/j.softx.2019.100345" target="_blank" onclick="return trackOutboundLink('https://doi.org/10.1016/j.softx.2019.100345');">AFF3CT: A Fast Forward Error Correction Toolbox!</a>,“ <i>SoftwareX</i>, 2019</strong>. <a title="PDF Article" href="https://hal.inria.fr/hal-02358306/file/Cassagne2019a%20-%20AFF3CT%3A%20A%20Fast%20Forward%20Error%20Correction%20Toolbox.pdf" target="_blank" onclick="return trackOutboundLink('https://hal.inria.fr/hal-02358306/file/Cassagne2019a%20-%20AFF3CT%3A%20A%20Fast%20Forward%20Error%20Correction%20Toolbox.pdf');"><i class="fas fa-file-pdf" aria-hidden="true"></i></a> <a title="Bibtex Entry" href="resources/bibtex/Cassagne2019a%20-%20AFF3CT:%20A%20Fast%20Forward%20Error%20Correction%20Toolbox.bib" target="_blank" onclick="return trackOutboundLink('resources/bibtex/Cassagne2019a%20-%20AFF3CT:%20A%20Fast%20Forward%20Error%20Correction%20Toolbox.bib');"><i class="fas fa-file-alt" aria-hidden="true"></i></a></p>
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<ul class="nav nav-tabs">
<li class="nav-item"><a class="nav-link" href="hof_turbo.html">Turbo</a></li>
<li class="nav-item"><a class="nav-link" href="hof_ldpc.html">LDPC</a></li>
<li class="nav-item"><a class="nav-link active" href="hof_polar.html">Polar</a></li>
</ul>
<div class="mb-4"></div>
<div id=polar-codes class="codes">
<div class="bs-example" data-example-id="panel-without-body-with-table">
<p class="lead"><strong>Successive Cancellation (SC)</strong></p>
<div class="table-responsive">
<table class="table sortable table-hover table-striped">
<thead>
<tr>
<th>Work</th>
<th id="year1">Year</th>
<th class="vl">Platform</th>
<th>Implem.</th>
<th><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Precision in bits">Pre.</span></th>
<th><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Inter frame level: number of frames computed in parallel">Inter</span></th>
<th><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Frame size"><math><mi>N</mi></math></span></th>
<th>
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Code rate:
<math>
<mi>R</mi>
<mo>=</mo>
<mfrac>
<mi>K</mi>
<mi>N</mi>
</mfrac>
</math>">
<math><mi>R</mi></math>
</span>
</th>
<th class="vl"><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Latency in micro seconds: time to decode one frame"><math><mi>Lat.</mi></math></span></th>
<th>
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Information throughput in Mbps:<br/>
<math>
<mi>Thr.</mi>
<mo>=</mo>
<mfrac>
<mrow>
<mi>N</mi>
<mo>×</mo>
<mi>R</mi>
<mo>×</mo>
<mi>Inter</mi>
</mrow>
<mi>Lat.</mi>
</mfrac>
</math>">
<math><mi>Thr.</mi></math>
</span>
</th>
<th class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Throughput under Normalized Decoding Cost:<br/>
<math>
<mi>TNDC</mi>
<mo>=</mo>
<mfrac>
<mrow>
<mrow><mi>Thr.</mi></mrow>
</mrow>
<mrow>
<mrow><mi>Cores</mi></mrow>
<mo>×</mo>
<mrow><mi>Freq.</mi></mrow>
<mo>×</mo>
<mrow><mi>SIMD</mi></mrow>
</mrow>
</mfrac>
</math>">
<math><mi>TNDC</mi></math>
</span>
</th>
<th>
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Energy-per-bit (in nano Joules): <br />
<math>
<mrow><msub><mi>E</mi><mi>d</mi></msub></mrow>
<mo>=</mo>
<mfrac>
<mrow>
<mi>TDP</mi>
</mrow>
<mrow>
<mi>Thr.</mi>
</mrow>
</mfrac>
<mo>×</mo>
<msup>
<mn>10</mn>
<mn>3</mn>
</msup>
</math>">
<math><msub><mi>E</mi><mi>d</mi></msub></math>
</span>
</th>
</tr>
</thead>
<tbody>
<tr>
<td><a class="tt" href="#ref1" data-toggle="tooltip" data-placement="top" data-html="true" title="P. Giard, G. Sarkis, C. Thibeault, and W. Gross, <b>Fast Software Polar Decoders</b>, <i>in Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)</i>, May 2014.">[1]</a></td>
<td>2014</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: CPU<br />
<u>Full name</u>: Core i7-2600 <br />
<u>Vendor</u>: Intel <br />
<u>Architecture</u>: Sandy Bridge<br />
<u>Frequency</u>: 3.40 GHz <br />
<u>SMX/Cores</u>: 4 (only 1 used) <br />
<u>SIMD type</u>: AVX (256-bit) <br />
<u>SIMD length</u>: 8 (32-bit/elmt) <br />
<u>TDP</u>: 95 Watts">
i7-2600
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Systematic SC algorithm + tree pruning optimizations (Rate 0, Rate 1, Rep, SPC)">Fast-SSC</span></td>
<td>32</td>
<td>1</td>
<td>32768</td>
<td>0.84</td>
<td class="vl">223</td>
<td>123.7</td>
<td class="vl">4.548</td>
<td>768</td>
</tr>
<tr>
<td><a class="tt" href="#ref1" data-toggle="tooltip" data-placement="top" data-html="true" title="P. Giard, G. Sarkis, C. Thibeault, and W. Gross, <b>Fast Software Polar Decoders</b>, <i>in Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)</i>, May 2014.">[1]</a></td>
<td>2014</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: CPU<br />
<u>Full name</u>: Core i7-2600 <br />
<u>Vendor</u>: Intel <br />
<u>Architecture</u>: Sandy Bridge<br />
<u>Frequency</u>: 3.40 GHz <br />
<u>SMX/Cores</u>: 4 (only 1 used) <br />
<u>SIMD type</u>: SSE4.1 (128-bit) <br />
<u>SIMD length</u>: 16 (8-bit/elmt) <br />
<u>TDP</u>: 95 Watts">
i7-2600
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Systematic SC algorithm + tree pruning optimizations (Rate 0, Rate 1, Rep, SPC)">Fast-SSC</span></td>
<td>8</td>
<td>1</td>
<td>32768</td>
<td>0.84</td>
<td class="vl">135</td>
<td>203.6</td>
<td class="vl">3.743</td>
<td>467</td>
</tr>
<tr>
<td><a class="tt" href="#ref2" data-toggle="tooltip" data-placement="top" data-html="true" title="B. Le Gal, C. Leroux and C. Jégo, <b>Software Polar Decoder on an Embedded Processor</b>, <i>in Proceedings of the IEEE International Workshop on Signal Processing Systems (SiPS)</i>, October 2014.">[2]</a></td>
<td>2014</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: CPU<br />
<u>Full name</u>: Tegra 3 dev. kit<br />
<u>Vendor</u>: ARM/Nvidia <br />
<u>Architecture</u>: Cortex-A9 MPCore <br />
<u>Frequency</u>: 1.30 GHz <br />
<u>SMX/Cores</u>: 4 (only 1 used)<br />
<u>SIMD type</u>: NEON (128-bit) <br />
<u>SIMD length</u>: 16 (8-bit/elmt) <br />
<u>TDP</u>: ~3 Watts">
Cortex-A9
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Systematic SC algorithm + tree pruning optimizations (Rate 0, Rate 1)">Fast-SSC</span></td>
<td>8</td>
<td>16</td>
<td>32768</td>
<td>0.90</td>
<td class="vl">16852</td>
<td>28.0</td>
<td class="vl">1.346</td>
<td>107</td>
</tr>
<tr>
<td><a class="tt" href="#ref4" data-toggle="tooltip" data-placement="top" data-html="true" title="G. Sarkis, P. Giard, C. Thibeault, and W. Gross, <b>Autogenerating Software Polar Decoders</b>, <i>in Proceedings of the IEEE Global Conference on Signal and Information Processing (GlobalSIP)</i>, December 2014.">[4]</a></td>
<td>2014</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: CPU<br />
<u>Full name</u>: Core i7-2600 <br />
<u>Vendor</u>: Intel <br />
<u>Architecture</u>: Sandy Bridge<br />
<u>Frequency</u>: 3.40 GHz <br />
<u>SMX/Cores</u>: 4 (only 1 used) <br />
<u>SIMD type</u>: AVX (256-bit) <br />
<u>SIMD length</u>: 8 (32-bit/elmt) <br />
<u>TDP</u>: 95 Watts">
i7-2600
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Systematic SC algorithm + tree pruning optimizations (Rate 0, Rate 1, Rep, SPC) + code source autogeneration">Fast-SSC</span></td>
<td>32</td>
<td>1</td>
<td>32768</td>
<td>0.84</td>
<td class="vl">125</td>
<td>219.8</td>
<td class="vl">8.081</td>
<td>432</td>
</tr>
<tr class="table-info">
<td class="vl"><a class="tt" href="#ref5" data-toggle="tooltip" data-placement="top" data-html="true" title="B. Le Gal, C. Leroux and C. Jégo, <b>Multi-Gb/s Software Decoding of Polar Codes</b>, <i>IEEE Transactions on Signal Processing (TSP)</i>, January 2015.">[5]</a></td>
<td>2015</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: CPU<br />
<u>Full name</u>: Core i7-4960HQ<br />
<u>Vendor</u>: Intel <br />
<u>Architecture</u>: Haswell <br />
<u>Frequency</u>: 3.60 GHz <br />
<u>SMX/Cores</u>: 4 (only 1 used)<br />
<u>SIMD type</u>: SSE4.2 (128-bit) <br />
<u>SIMD length</u>: 16 (8-bit/elmt) <br />
<u>TDP</u>: 47 Watts">
i7-4960HQ
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Systematic SC algorithm + tree pruning optimizations (Rate 0, Rate 1)">Fast-SSC</span></td>
<td>8</td>
<td>16</td>
<td>32768</td>
<td>0.90</td>
<td class="vl">337</td>
<td>1400.0</td>
<td class="vl">24.306</td>
<td>34</td>
</tr>
<tr class="table-info">
<td class="vl"><a class="tt" href="#ref6" data-toggle="tooltip" data-placement="top" data-html="true" title="A. Cassagne, B. Le Gal, C. Leroux, O. Aumage and D. Barthou, <b>An Efficient, Portable and Generic Library for Successive Cancellation Decoding of Polar Codes</b>, <i>in Proceedings of the the Springer International Workshop on Languages and Compilers for Parallel Computing (LCPC)</i>, September 2015.">[6]</a></td>
<td>2015</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: CPU<br />
<u>Full name</u>: Xeon E3-1225<br />
<u>Vendor</u>: Intel <br />
<u>Architecture</u>: Sandy Bridge <br />
<u>Frequency</u>: 3.10 GHz <br />
<u>SMX/Cores</u>: 4 (only 1 used)<br />
<u>SIMD type</u>: AVX (256-bit) <br />
<u>SIMD length</u>: 8 (32-bit/elmt) <br />
<u>TDP</u>: 95 Watts">
E3-1225
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Systematic SC algorithm + tree pruning optimizations (Rate 0, Rate 1, Rep, SPC) + code source autogeneration">Fast-SSC</span></td>
<td>32</td>
<td>1</td>
<td>32768</td>
<td>0.84</td>
<td class="vl">114</td>
<td>241.0</td>
<td class="vl">9.718</td>
<td>394</td>
</tr>
<tr class="table-info">
<td class="vl"><a class="tt" href="#ref6" data-toggle="tooltip" data-placement="top" data-html="true" title="A. Cassagne, B. Le Gal, C. Leroux, O. Aumage and D. Barthou, <b>An Efficient, Portable and Generic Library for Successive Cancellation Decoding of Polar Codes</b>, <i>in Proceedings of the the Springer International Workshop on Languages and Compilers for Parallel Computing (LCPC)</i>, September 2015.">[6]</a></td>
<td>2015</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: CPU<br />
<u>Full name</u>: Xeon E3-1225<br />
<u>Vendor</u>: Intel <br />
<u>Architecture</u>: Sandy Bridge <br />
<u>Frequency</u>: 3.10 GHz <br />
<u>SMX/Cores</u>: 4 (only 1 used)<br />
<u>SIMD type</u>: SSE4.2 (128-bit) <br />
<u>SIMD length</u>: 16 (8-bit/elmt) <br />
<u>TDP</u>: 95 Watts">
E3-1225
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Systematic SC algorithm + tree pruning optimizations (Rate 0, Rate 1, Rep, SPC) + code source autogeneration">Fast-SSC</span></td>
<td>8</td>
<td>16</td>
<td>32768</td>
<td>0.83</td>
<td class="vl">370</td>
<td>1180.0</td>
<td class="vl">23.790</td>
<td>81</td>
</tr>
<tr>
<td><a class="tt" href="#ref8" data-toggle="tooltip" data-placement="top" data-html="true" title="P. Giard, G. Sarkis, C. Leroux, C. Thibeault, and W. J. Gross, <b>Low-Latency Software Polar Decoders</b>, <i>Springer Journal of Signal Processing Systems (JSPS)</i>, July 2016.">[8]</a></td>
<td>2016</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: CPU<br />
<u>Full name</u>: Core i7-4770S<br />
<u>Vendor</u>: Intel <br />
<u>Architecture</u>: Haswell <br />
<u>Frequency</u>: 3.10 GHz <br />
<u>SMX/Cores</u>: 4 (only 1 used)<br />
<u>SIMD type</u>: AVX2 (256-bit) <br />
<u>SIMD length</u>: 32 (8-bit/elmt) <br />
<u>TDP</u>: 65 Watts">
i7-4770S
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Systematic SC algorithm + tree pruning optimizations (Rate 0, Rate 1, Rep, SPC) + code source autogeneration">Fast-SSC</span></td>
<td>8</td>
<td>1</td>
<td>32768</td>
<td>0.84</td>
<td class="vl">31</td>
<td>886.0</td>
<td class="vl">8.931</td>
<td>73</td>
</tr>
<tr>
<td><a class="tt" href="#ref8" data-toggle="tooltip" data-placement="top" data-html="true" title="P. Giard, G. Sarkis, C. Leroux, C. Thibeault, and W. J. Gross, <b>Low-Latency Software Polar Decoders</b>, <i>Springer Journal of Signal Processing Systems (JSPS)</i>, July 2016.">[8]</a></td>
<td>2016</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: CPU <br />
<u>Full name</u>: Exynos 4412 <br />
<u>Vendor</u>: ARM/Samsung <br />
<u>Architecture</u>: Cortex-A9 MPCore <br />
<u>Frequency</u>: 1.70 GHz <br />
<u>SMX/Cores</u>: 4 (only 1 used)<br />
<u>SIMD type</u>: NEON (128-bit) <br />
<u>SIMD length</u>: 16 (8-bit/elmt) <br />
<u>TDP</u>: ~3 Watts">
Cortex-A9
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Systematic SC algorithm + tree pruning optimizations (Rate 0, Rate 1, Rep, SPC) + code source autogeneration">Fast-SSC</span></td>
<td>8</td>
<td>1</td>
<td>32768</td>
<td>0.90</td>
<td class="vl">361</td>
<td>81.7</td>
<td class="vl">3.003</td>
<td>37</td>
</tr>
<tr>
<td><a class="tt" href="#ref8" data-toggle="tooltip" data-placement="top" data-html="true" title="P. Giard, G. Sarkis, C. Leroux, C. Thibeault, and W. J. Gross, <b>Low-Latency Software Polar Decoders</b>, <i>Springer Journal of Signal Processing Systems (JSPS)</i>, July 2016.">[8]</a></td>
<td>2016</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: GPU<br />
<u>Full name</u>: Tesla K20c<br />
<u>Vendor</u>: Nvidia <br />
<u>Architecture</u>: Kepler<br />
<u>Frequency</u>: 0.71 GHz<br />
<u>SMX/Cores</u>: 13<br />
<u>SIMD type</u>: SIMT<br />
<u>SIMD length</u>: 192<br />
<u>TDP</u> : 225 Watts">
Tesla K20c
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Systematic SC algorithm + tree pruning optimizations (Rate 0, Rate 1, Rep, SPC) + code source autogeneration">Fast-SSC</span></td>
<td>32</td>
<td>832</td>
<td>4096</td>
<td>0.90</td>
<td class="vl">9400</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Following the formula, the throughput should be lower but the authors performed a specific data transfers overlapping with CUDA streams allowing to reach higher throughput.">1043.0</span></td>
<td class="vl">0.589</td>
<td>216</td>
</tr>
<tr class="table-info">
<td class="vl"><a class="tt" href="#ref9" data-toggle="tooltip" data-placement="top" data-html="true" title="A. Cassagne, O. Aumage, C. Leroux, D. Barthou and B. Le Gal, <b>Energy Consumption Analysis of Software Polar Decoders on Low Power Processors</b>, <i>in Proceedings of the IEEE European Signal Processing Conference (EUSIPCO)</i>, September 2016.">[9]</a></td>
<td>2016</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: CPU<br />
<u>Full name</u>: Core i7-4850HQ<br />
<u>Vendor</u>: Intel <br />
<u>Architecture</u>: Haswell <br />
<u>Frequency</u>: 3.30 GHz <br />
<u>SMX/Cores</u>: 4 (only 1 used)<br />
<u>SIMD type</u>: SSE4.2 (128-bit) <br />
<u>SIMD length</u>: 16 (8-bit/elmt) <br />
<u>TDP</u>: 47 Watts">
i7-4850HQ
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Systematic SC algorithm + tree pruning optimizations (Rate 0, Rate 1, Rep, SPC)">Fast-SSC</span></td>
<td>8</td>
<td>1</td>
<td>32768</td>
<td>0.83</td>
<td class="vl">47</td>
<td>580.0</td>
<td class="vl">10.984</td>
<td>81</td>
</tr>
<tr class="table-info">
<td class="vl"><a class="tt" href="#ref9" data-toggle="tooltip" data-placement="top" data-html="true" title="A. Cassagne, O. Aumage, C. Leroux, D. Barthou and B. Le Gal, <b>Energy Consumption Analysis of Software Polar Decoders on Low Power Processors</b>, <i>in Proceedings of the IEEE European Signal Processing Conference (EUSIPCO)</i>, September 2016.">[9]</a></td>
<td>2016</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: CPU<br />
<u>Full name</u>: Juno dev. kit<br />
<u>Vendor</u>: ARM <br />
<u>Architecture</u>: Cortex-A57 MPCore <br />
<u>Frequency</u>: 1.10 GHz <br />
<u>SMX/Cores</u>: 2 (only 1 used)<br />
<u>SIMD type</u>: NEON (128-bit) <br />
<u>SIMD length</u>: 16 (8-bit/elmt) <br />
<u>TDP</u>: ~2 Watts">
Cortex-A57
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Systematic SC algorithm + tree pruning optimizations (Rate 0, Rate 1, Rep, SPC)">Fast-SSC</span></td>
<td>8</td>
<td>1</td>
<td>32768</td>
<td>0.83</td>
<td class="vl">374</td>
<td>73.0</td>
<td class="vl">4.148</td>
<td>27</td>
</tr>
<tr>
<td><a class="tt" href="#ref11" data-toggle="tooltip" data-placement="top" data-html="true" title="Y. Lo, and R. Liu, <b>High Throughput GPU Polar Decoder</b>, <i>in Proceedings of the IEEE International Conference on Computer and Communications (ICCC)</i>, October 2016.">[11]</a></td>
<td>2016</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: GPU<br />
<u>Full name</u>: Tesla K20c<br />
<u>Vendor</u>: Nvidia <br />
<u>Architecture</u>: Kepler<br />
<u>Frequency</u>: 0.71 GHz<br />
<u>SMX/Cores</u>: 13<br />
<u>SIMD type</u>: SIMT<br />
<u>SIMD length</u>: 192<br />
<u>TDP</u> : 225 Watts">
Tesla K20c
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Systematic SC algorithm + tree pruning optimizations (Rate 0, Rate 1, Rep, SPC) + code source autogeneration">Fast-SSC</span></td>
<td>32</td>
<td>-</td>
<td>256</td>
<td>0.50</td>
<td class="vl">-</td>
<td>395.0</td>
<td class="vl">0.223</td>
<td>570</td>
</tr>
</tbody>
</table>
</div>
</div>
<div class="mb-4"></div>
<div class="bs-example" data-example-id="panel-without-body-with-table">
<p class="lead"><strong>Soft CANcellation (SCAN)</strong></p>
<div class="table-responsive">
<table class="table sortable table-hover table-striped">
<thead>
<tr>
<th>Work</th>
<th id="year2">Year</th>
<th class="vl">Platform</th>
<th>Implem.</th>
<th><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Precision in bits">Pre.</span></th>
<th><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Inter frame level: number of frames computed in parallel">Inter</span></th>
<th><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Frame size"><math><mi>N</mi></math></span></th>
<th>
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Code rate:
<math>
<mi>R</mi>
<mo>=</mo>
<mfrac>
<mi>K</mi>
<mi>N</mi>
</mfrac>
</math>">
<math><mi>R</mi></math>
</span>
</th>
<th><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Number of iteration in the decoding process"><math><mi>i</mi></math></span></th>
<th class="vl"><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Latency in micro seconds: time to decode one frame"><math><mi>Lat.</mi></math></span></th>
<th>
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Information throughput in Mbps:<br/>
<math>
<mi>Thr.</mi>
<mo>=</mo>
<mfrac>
<mrow>
<mi>N</mi>
<mo>×</mo>
<mi>R</mi>
<mo>×</mo>
<mi>Inter</mi>
</mrow>
<mi>Lat.</mi>
</mfrac>
</math>">
<math><mi>Thr.</mi></math>
</span>
</th>
<th class="vl" id="nthr2">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Normalized throughput in Mbps:<br/>
<math>
<mi>NThr.</mi>
<mo>=</mo>
<mfrac>
<mrow>
<mrow><mi>Thr.</mi></mrow>
<mo>×</mo>
<mrow><mi>i</mi></mrow>
</mrow>
<mrow>
<mi>4</mi>
</mrow>
</mfrac>
</math>">
<math><mi>NThr.</mi></math>
</span>
</th>
<th>
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Throughput under Normalized Decoding Cost:<br/>
<math>
<mi>TNDC</mi>
<mo>=</mo>
<mfrac>
<mrow>
<mi>NThr.</mi>
</mrow>
<mrow>
<mrow><mi>Cores</mi></mrow>
<mo>×</mo>
<mrow><mi>Freq.</mi></mrow>
<mo>×</mo>
<mrow><mi>SIMD</mi></mrow>
</mrow>
</mfrac>
</math>">
<math><mi>TNDC</mi></math>
</span>
</th>
<th>
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Energy-per-bit (in nano Joules): <br />
<math>
<mrow><msub><mi>E</mi><mi>d</mi></msub></mrow>
<mo>=</mo>
<mfrac>
<mi>TDP</mi>
<mi>NThr.</mi>
</mfrac>
<mo>×</mo>
<msup>
<mn>10</mn>
<mn>3</mn>
</msup>
</math>">
<math><msub><mi>E</mi><mi>d</mi></msub></math>
</span>
</th>
</tr>
</thead>
<tbody>
<tr>
<td><a class="tt" href="#ref14" data-toggle="tooltip" data-placement="top" data-html="true" title="B. Le Gal, C. Leroux and C. Jégo, <b>High-Performance Software Implementation of SCAN Decoders for Polar Codes</b>, <i>Springer Annals of Telecommunications</i>, June 2018.">[14]</a></td>
<td>2018</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: CPU<br />
<u>Full name</u>: Core i7-4960HQ<br />
<u>Vendor</u>: Intel <br />
<u>Architecture</u>: Haswell <br />
<u>Frequency</u>: 3.60 GHz <br />
<u>SMX/Cores</u>: 4 (only 1 used)<br />
<u>SIMD type</u>: AVX2 (256-bit) <br />
<u>SIMD length</u>: 32 (8-bit/elmt) <br />
<u>TDP</u>: 47 Watts">
i7-4960HQ
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="SCAN algorithm + tree pruning optimizations (Rate 0, Rate 1)">Fast-SCAN</span></td>
<td>8</td>
<td>1</td>
<td>32768</td>
<td>0.84</td>
<td>1</td>
<td class="vl">56</td>
<td>490.0</td>
<td class="vl">122.5</td>
<td>1.06</td>
<td>384</td>
</tr>
<tr>
<td><a class="tt" href="#ref14" data-toggle="tooltip" data-placement="top" data-html="true" title="B. Le Gal, C. Leroux and C. Jégo, <b>High-Performance Software Implementation of SCAN Decoders for Polar Codes</b>, <i>Springer Annals of Telecommunications</i>, June 2018.">[14]</a></td>
<td>2018</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: CPU<br />
<u>Full name</u>: Core i7-4960HQ<br />
<u>Vendor</u>: Intel <br />
<u>Architecture</u>: Haswell <br />
<u>Frequency</u>: 3.60 GHz <br />
<u>SMX/Cores</u>: 4 (only 1 used)<br />
<u>SIMD type</u>: AVX2 (256-bit) <br />
<u>SIMD length</u>: 32 (8-bit/elmt) <br />
<u>TDP</u>: 47 Watts">
i7-4960HQ
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="SCAN algorithm + tree pruning optimizations (Rate 0, Rate 1)">Fast-SCAN</span></td>
<td>8</td>
<td>32</td>
<td>32768</td>
<td>0.84</td>
<td>1</td>
<td class="vl">1601</td>
<td>550.0</td>
<td class="vl">137.5</td>
<td>1.19</td>
<td>342</td>
</tr>
</tbody>
</table>
</div>
</div>
<div class="mb-4"></div>
<div class="bs-example" data-example-id="panel-without-body-with-table">
<p class="lead"><strong>Successive Cancellation List (SCL)</strong></p>
<div class="table-responsive">
<table class="table sortable table-hover table-striped">
<thead>
<tr>
<th>Work</th>
<th id="year3">Year</th>
<th class="vl">Platform</th>
<th>Implem.</th>
<th><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Precision in bits">Pre.</span></th>
<th><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Inter frame level: number of frames computed in parallel">Inter</span></th>
<th><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Frame size"><math><mi>N</mi></math></span></th>
<th>
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Code rate:
<math>
<mi>R</mi>
<mo>=</mo>
<mfrac>
<mi>K</mi>
<mi>N</mi>
</mfrac>
</math>">
<math><mi>R</mi></math>
</span>
</th>
<th><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Number of list in the SCL decoding process"><math><mi>L</mi></math></span></th>
<th class="vl"><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Latency in micro seconds: time to decode one frame"><math><mi>Lat.</mi></math></span></th>
<th>
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Information throughput in Mbps:<br/>
<math>
<mi>Thr.</mi>
<mo>=</mo>
<mfrac>
<mrow>
<mi>N</mi>
<mo>×</mo>
<mi>R</mi>
<mo>×</mo>
<mi>Inter</mi>
</mrow>
<mi>Lat.</mi>
</mfrac>
</math>">
<math><mi>Thr.</mi></math>
</span>
</th>
<th class="vl" id="nthr3">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Normalized throughput in Mbps:<br/>
<math>
<mi>NThr.</mi>
<mo>=</mo>
<mfrac>
<mrow>
<mi>Thr.</mi>
<mo>×</mo>
<mi>L</mi>
</mrow>
<mrow>
<mi>8</mi>
</mrow>
</mfrac>
</math>">
<math><mi>NThr.</mi></math>
</span>
</th>
<th>
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Throughput under Normalized Decoding Cost:<br/>
<math>
<mi>TNDC</mi>
<mo>=</mo>
<mfrac>
<mrow>
<mi>NThr.</mi>
</mrow>
<mrow>
<mrow><mi>Cores</mi></mrow>
<mo>×</mo>
<mrow><mi>Freq.</mi></mrow>
<mo>×</mo>
<mrow><mi>SIMD</mi></mrow>
</mrow>
</mfrac>
</math>">
<math><mi>TNDC</mi></math>
</span>
</th>
<th>
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Energy-per-bit (in nano Joules): <br />
<math>
<mrow><msub><mi>E</mi><mi>d</mi></msub></mrow>
<mo>=</mo>
<mfrac>
<mrow>
<mi>TDP</mi>
</mrow>
<mrow>
<mi>NThr.</mi>
</mrow>
</mfrac>
<mo>×</mo>
<msup>
<mn>10</mn>
<mn>3</mn>
</msup>
</math>">
<math><msub><mi>E</mi><mi>d</mi></msub></math>
</span>
</th>
</tr>
</thead>
<tbody>
<tr>
<td><a class="tt" href="#ref3" data-toggle="tooltip" data-placement="top" data-html="true" title="G. Sarkis, P. Giard, A. Vardy, C. Thibeault, and W. Gross, <b>Increasing the Speed of Polar List Decoders</b>, <i>in Proceedings of the IEEE International Workshop on Signal Processing Systems (SiPS)</i>, October 2014.">[3]</a></td>
<td>2014</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: CPU<br />
<u>Full name</u>: Core i7-2600 <br />
<u>Vendor</u>: Intel <br />
<u>Architecture</u>: Sandy Bridge<br />
<u>Frequency</u>: 3.40 GHz <br />
<u>SMX/Cores</u>: 4 (only 1 used) <br />
<u>SIMD type</u>: AVX (256-bit) <br />
<u>SIMD length</u>: 8 (32-bit/elmt) <br />
<u>TDP</u>: 95 Watts">
i7-2600
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="SCL algorithm + tree pruning optimizations (Rate 0, Rate 1 Chase decoding) + CRC">SSC-List-CRC</span></td>
<td>32</td>
<td>1</td>
<td>2048</td>
<td>0.84</td>
<td>32</td>
<td class="vl">3300</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Using a CRC and an adaptive decoding (Fast-SSC + CRC + SSC-List-CRC) allows to reach <b>54.0 Mbps at 4.5 dB</b>.">0.52</span></td>
<td class="vl">2.08</td>
<td>0.076</td>
<td>45673</td>
</tr>
<tr>
<td><a class="tt" href="#ref7" data-toggle="tooltip" data-placement="top" data-html="true" title="G. Sarkis, P. Giard, A. Vardy, C. Thibeault, and W. J. Gross, <b>Fast List Decoders for Polar Codes</b>,” <i>IEEE Journal on Selected Areas in Communications (JSAC)</i>, February 2016.">[7]</a></td>
<td>2016</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: CPU<br />
<u>Full name</u>: Core i7-2600 <br />
<u>Vendor</u>: Intel <br />
<u>Architecture</u>: Sandy Bridge<br />
<u>Frequency</u>: 3.40 GHz <br />
<u>SMX/Cores</u>: 4 (only 1 used) <br />
<u>SIMD type</u>: AVX (256-bit) <br />
<u>SIMD length</u>: 8 (32-bit/elmt) <br />
<u>TDP</u>: 95 Watts">
i7-2600
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="SCL algorithm + tree pruning optimizations (Rate 0, Rate 1 Chase decoding, Rep, SPC) + CRC + code source autogeneration">Fast-SSC-List-CRC</span></td>
<td>32</td>
<td>1</td>
<td>2048</td>
<td>0.84</td>
<td>32</td>
<td class="vl">433</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Using a CRC and an adaptive decoding (Fast-SSC + CRC + Fast-SSC-List-CRC) allows to reach <b>196.0 Mbps at 4.5 dB</b>.">4.00</span></td>
<td class="vl">16.0</td>
<td>0.588</td>
<td>5938</td>
</tr>
<tr>
<td><a class="tt" href="#ref10" data-toggle="tooltip" data-placement="top" data-html="true" title="Y. Shen, C. Zhang, J. Yang, S. Zhang, and X. You, <b>Low-Latency Software Successive Cancellation List Polar Decoder using Stage-located Copy</b>, <i>in Proceedings of the IEEE International Conference on Digital Signal Processing (DSP)</i>, October 2016.">[10]</a></td>
<td>2016</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: CPU<br />
<u>Full name</u>: Core i7-4790K <br />
<u>Vendor</u>: Intel <br />
<u>Architecture</u>: Haswell<br />
<u>Frequency</u>: 4.00 GHz <br />
<u>SMX/Cores</u>: 4 (only 1 used) <br />
<u>SIMD type</u>: AVX2 (256-bit) <br />
<u>SIMD length</u>: 8 (32-bit/elmt) <br />
<u>TDP</u>: 88 Watts">
i7-4790K
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="SCL algorithm + CRC">SC-List-CRC</span></td>
<td>32</td>
<td>1</td>
<td>2048</td>
<td>0.84</td>
<td>32</td>
<td class="vl">1573</td>
<td>1.10</span></td>
<td class="vl">4.40</td>
<td>0.138</td>
<td>20000</td>
</tr>
<tr>
<td class="vl"><a class="tt" href="#ref12" data-toggle="tooltip" data-placement="top" data-html="true" title="S. Cammerer, B. Leible, M. Stahl, J. Hoydis and S. ten Brink, <b>Combining Belief Propagation and Successive Cancellation List Decoding of Polar Codes on a GPU Platform</b>, <i>in Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)</i>, March 2017.">[12]</a></td>
<td>2017</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: GPU <br />
<u>Full name</u>: GeForce GTX 980 Ti <br />
<u>Vendor</u>: Nvidia <br />
<u>Architecture</u>: Maxwell <br />
<u>Frequency</u>: 1.00 GHz <br />
<u>SMX/Cores</u>: 22 <br />
<u>SIMD type</u>: SIMT <br />
<u>SIMD length</u>: 128 <br />
<u>TDP</u>: 250 Watts">
GTX 980 Ti
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Belief Propagation (BP) + SCL algorithm + CRC">BP+SC-List-CRC</span></td>
<td>32</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Deduced from the latency and the throughput">5</span></td>
<td>4096</td>
<td>0.50</td>
<td>32</td>
<td class="vl">1000000</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Using a CRC and a BP decoding first (BP + CRC + SCL-CRC) allows to reach <b>34.0 Mbps at 4.0 dB</b>.">0.01</span></td>
<td class="vl">0.04</td>
<td>0.000001</td>
<td>6250000</td>
</tr>
<tr>
<td class="vl"><a class="tt" href="#ref13" data-toggle="tooltip" data-placement="top" data-html="true" title="X. Han, R. Liu, Z. Liu and L. Zhao, <b>Successive-Cancellation List Decoder of Polar Codes Based on GPU</b>, <i>in Proceedings of the IEEE International Conference on Computer and Communications (ICCC)</i>, December 2017.">[13]</a></td>
<td>2017</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: GPU <br />
<u>Full name</u>: GeForce GTX 980 <br />
<u>Vendor</u>: Nvidia <br />
<u>Architecture</u>: Maxwell <br />
<u>Frequency</u>: 1.17 GHz <br />
<u>SMX/Cores</u>: 16 <br />
<u>SIMD type</u>: SIMT <br />
<u>SIMD length</u>: 128 <br />
<u>TDP</u>: 165 Watts">
GTX 980
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="SCL algorithm">SC-List</span></td>
<td>32/16</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Deduced from the latency and the throughput">1310</span></td>
<td>4096</td>
<td>0.50</td>
<td>32</td>
<td class="vl"><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Not including the memory data transfers time between CPU and GPU">111900</span></td>
<td>24.0</td>
<td class="vl">96.0</td>
<td>0.040</td>
<td>1719</td>
</tr>
<tr>
<td class="vl"><a class="tt" href="#ref13" data-toggle="tooltip" data-placement="top" data-html="true" title="X. Han, R. Liu, Z. Liu and L. Zhao, <b>Successive-Cancellation List Decoder of Polar Codes Based on GPU</b>, <i>in Proceedings of the IEEE International Conference on Computer and Communications (ICCC)</i>, December 2017.">[13]</a></td>
<td>2017</td>
<td class="vl">
<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="
<u>Device type</u>: GPU <br />
<u>Full name</u>: GeForce GTX TITAN X <br />
<u>Vendor</u>: Nvidia <br />
<u>Architecture</u>: Maxwell <br />
<u>Frequency</u>: 1.00 GHz <br />
<u>SMX/Cores</u>: 24 <br />
<u>SIMD type</u>: SIMT <br />
<u>SIMD length</u>: 128 <br />
<u>TDP</u>: 250 Watts">
GTX TITAN X
</span>
</td>
<td><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="SCL algorithm">SC-List</span></td>