Fast GPIO Interface (Dedicated GPIO)

[yanshay]

ESP32S3 supports Fast GPIO (also called Dedicated GPIO). However, this is not yet supported by esp-hal.
It is documented in - esp32s3 technical reference (https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf).
The technique is to connect the fast-gpio peripheral signals to the relevant gpio, and then use asm code to set the register using dedicated asm instructions.

These are the relevant pages in the document.

• Page 46 - Description of the interface
• Page 465 - How to set Peripheral output via GPIO Matrix
• Page 479 - Peripheral signals (pro_alonegpio_xxxx for core0/ProCore)

I went ahead and tried to implement it directly with the registers and asm code but without success.
So ... I'm posting here, in case someone can help me get it to work. Any assistance would be appreciated.
Once it's working I think it would be quite easy to get it into esp-hal.

This is what I did:
I followed instructions in page 465, trying to connect bit 0 of the fast gpio to gpio45 (which I can get a visual on/off on my board).
221 is the value of pro_alonegpio_out0 - so bit 0 of the fast gpio out peripheral.

    // GPIO_FUNCx_OUT_SEL_CFG
    unsafe { &*hal::peripherals::GPIO::PTR }.func_out_sel_cfg[45 as usize].modify(|_, w| unsafe {
        w.out_sel()
          .bits(221)
          .inv_sel()
          .bit(false)
          .oen_sel()
          .bit(false)
          .oen_inv_sel()
          .bit(false)
    });
 
    // GPIO_ENABLE_REG
    unsafe { &*hal::peripherals::GPIO::PTR }.enable_w1ts.write(|w| unsafe {
        w.bits(0x2000)
    });


    // IO_MUX_MCU_SEL
    unsafe { &*hal::peripherals::IO_MUX::PTR}.gpio[45].modify(|_, w| unsafe { w.mcu_sel().bits(1) }); // set to Function 1

Then to set the bit I used (as explained in forums and in esp-hal code)

        unsafe { core::arch::asm!("wur.gpio_out {0}", in(reg) 0xffu32)  };

        unsafe { core::arch::asm!("wur.gpio_out {0}", in(reg) 0x0u32)  };

Note that I could not get the ee.set_bit_gpio_out and similar asm instructions (mentioned in the tech reference) to compile in rust.

[yanshay]

I managed to solve this.
The issue was with the asm code which for some reason doesn't work, don't know how it work in esp-idf.
I managed to get it to work with the mask command:
unsafe { core::arch::asm!("ee.wr_mask_gpio_out {0}, {1}", in(reg) 0x00, in(reg) 0x01) };
I just hope it's as fast as the non masked version.

[bjoernQ]

Just for completeness:

More chips support dedicated GPIO (S2) - on our RISCV chips it's supported via the cpu_gpio_* CSRs

[yanshay]

Do you know to say why the wur.gpio_out doesn't work on esp32s3? That's the code used in esp-idf for esp32s3.
Maybe a compile issue?

https://github.com/espressif/esp-idf/blob/5524b692ee5d04d7a1000eb0c41640746fc67f3c/components/hal/esp32s3/include/hal/dedic_gpio_cpu_ll.h#L43C4-L43C4

__attribute__((always_inline))
static inline void dedic_gpio_cpu_ll_write_all(uint32_t value)
{
    asm volatile("wur.gpio_out %0"::"r"(value):);
}

[MabezDev]

What do you mean by doesn't work? Doesn't compile, or doesn't work as expected?

[yanshay]

It does compile. It doesn't work as expected.

I send the data and it doesn't modify the gpio's. With ee.wr_mask_gpio_out it works as expected, so it's not some device setup issue.

[yanshay]

And while at it, two commands from the technical reference didn't compile:
EE.SET_BIT_GPIO_OUT
EE.CLR_BIT_GPIO_OUT

mentioned in: https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf

• page 46, 76, 119

[bjoernQ]

I guess it's because in Rust we use LLVM while ESP-IDF uses GCC - maybe @MabezDev knows more details?

[yuiiio]

with esp32s2
also can't get wr_mask_gpio_out, wur.gpio_out, {set,clr}_bit_gpio_out even use asm!()
sorry I forgot to using xtensa-esp32s2-elf-clang-objdump
(esp32s2 and wur.gpio_out, wr_mask_gpio_out works correct (need manualy settings dedicated gpio register))