[BUG] Wrong behavior for handing Invalid NaN-boxed for Single-Precision Floating-Point division

[riscv914]

Is there an existing CVA6 bug for this?

• I have searched the existing bug issues

Bug Description

Executing Single-Precision Floating-Point division by an invalid NaN-boxed value (a value that most significant 32 bits are not set to 1) will result in an invalid value and raise the flag for dividing by zero while based on specification, the result should be a 32-bit canonical NaN, and divide by zero should not be raised.
Reference: https://github.com/riscv/riscv-isa-manual/blob/main/src/d-st-ext.adoc#nan-boxing-of-narrower-values

Execute following instruction:

int main(void){
    asm volatile ("lui     t5, 0xbd131");
    asm volatile ("fmv.w.x ft3, t5"); // ft3 = 0xffffffffbd131000
    asm volatile ("lui     s4, 0xee72f");
    asm volatile ("fmv.w.x fa7, s4"); // ft7 = 0xffffffffee72f000
    asm volatile ("fcvt.d.l fa7, s4"); // ft7 = 0xc1b18d1000000000
    asm volatile ("fdiv.s  ft3, ft3, fa7"); // ft3 = 0xffffffffff800000
    asm volatile ("csrr    a4, fflags"); // a4 = 0x0000000000000008
}

However, if you execute same code on Spike you will get a4=0x0 and ft3=0xffffffff7fc00000.

- Spike version: `1.1.1-dev`
- version: `CVA6 commit: 7435cb310ee98c246edd15d00ec236ad2c6ff490`
- OS: `CentOS Linux release 7.9.2009 kernel: 5.15.0-78-generic`
- Simulator: `VCS_2023`