[BUG] CVA6 core throw Store Address Misaligned
while address for Load-Reserved
is misaligned
#2455
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Labels
notCV32A65X
It is not an CV32A65X issue
PARAM:AMO
Atomic extension
Type:Bug
For bugs in the RTL, Documentation, Verification environment or Tool and Build system
Is there an existing CVA6 bug for this?
Bug Description
When executing Load-Reserved instructions (e.g.
LR.D
) with a misaligned address, CVA6 core throwStore Address Misaligned
while it should throwLoad Address Misaligned
.To reproduce, execute following instruction:
However, if you execute same code on Spike you will get
trap_load_address_misaligned
exception.The text was updated successfully, but these errors were encountered: