Investigation additonal of external trigger to scope PCB

[rpcope1]

The PCB appears to be provisioned to add an y wexternal trigger, though it did not make it out of the factory with one. I should do severals things:

• Verify that the trace for the trigger interfaces with the FX2LP and determine what pin.
• Make a BOM to determine what additional parts are needed to add this
• Investigate adding ext trigger to firmware and driver.

[jhoenicke]

If you are tracing the pins of the FX2LP, can you trace where ports A,B,C,D lead to?

• Port A, bit 7 should go to the squarewave generator.
• Port C, bit 0-1 should go to the LED.
• Port C, bit 2-7 should go to the analog multiplexers.
• Port B,D should go to the ADC output.
• For triggering probably some RDY pin is used.
• Are the CTL pins connected?
• What are Port A 0-6 connected to?

[rpcope1]

Yeah, I'll see if I can't do it when I get home from work today.

On Thu, Apr 30, 2015 at 3:00 AM, Jochen Hoenicke [email protected]
wrote:

If you are tracing the pins of the FX2LP, can you trace where ports
A,B,C,D lead to?

• Port A, bit 7 should go to the squarewave generator.
• Port C, bit 0-1 should go to the LED.
• Port C, bit 2-7 should go to the analog multiplexers.
• Port B,D should go to the ADC output.
• For triggering probably some RDY pin is used.
• Are the CTL pins connected?
• What are Port A 0-6 connected to?

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#14 (comment)
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[rpcope1]

A7 -> R16 which is the entry point to an RC network the forms the output for the wave generator.
C0 and C1 are hooked up to top and middle pin on the LED through 500 ohm resistors. Bottom pin (J1) of LED is grounded.
C2 -> S0 on U6 (74HC4051, CH1)
C3 -> S1 on U6
C4 -> S2 on U6
C5 -> S0 on U10 (74HC4051, CH2)
C6 -> S1 on U10
C7 -> S2 on U10
Trigger -> R13 (this resistor is missing) -> T0 on FX2LP

[rpcope1]

FX2LP D0-7 -> D0-7B on the AD9288
FX2LP B0-7 -> D0-7A on the AD9288

[rpcope1]

The CTL pins CTL0-5 have no traces running away from them. There's also no unknown vias nearby on the other side of the board, so it would appear as though they're not attached to anything.

[rpcope1]

Ok, so finally port A, other than pin 7: there's again no traces leaving any of the pins, and almost no vias in that region on the opposite side of the board, so it doesn't look like they're attached anywhere.

[rpcope1]

Also interesting, port E0-5 are attached to some holes for a 6 pin header on the board (JP2).

[baruch]

How does the ADC gets the clock input? There should have been some pin from the FX2LP to the ADC clock imo.

Edit: There are two clock inputs, one for each port to the ADC. From the available images I can't see where it is connected though.

[rpcope1]

I think CLKOUT on the FX2LP is routed to the ADC, but I'll confirm when I
get home.

On Fri, May 1, 2015 at 10:40 AM, Baruch Even [email protected]
wrote:

How does the ADC gets the clock input? There should have been some pin
from the FX2LP to the ADC clock imo.

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#14 (comment)
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[jhoenicke]

T0 is timer 0 input clock. So one can count the pulses and trigger a timer interrupt after a specified number of pulses. I'm not sure if this is useful for triggering.

I have no idea what E0-E5 are for. The firmware contains no code to access these registers. Maybe related to waveform debugging?

I think the ADC should be triggerred by either IFCLK or CTL2. 48/30 MHz mode enables clock output on IFCLK and keeps CTL2 to 1. Lower modi switch CTL2 in the wave form for every sample and disable clock output in IFCONFIG. Are you sure CTL2 is not connected?

In stock firmware 24 MHz was broken and sampled with 48 MHz, while disabling IFCLK and toggling CTL2 with 16 MHz (ok, only after patching the right waveform). The result was that there were always 3 identical samples, so CTL2 should have effects.

[rpcope1]

I'll look again, I probably missed something there on CTL2.

On Fri, May 1, 2015 at 11:43 AM, Jochen Hoenicke [email protected]
wrote:

T0 is timer 0 input clock. So one can count the pulses and trigger a timer
interrupt after a specified number of pulses. I'm not sure if this is
useful for triggering.

I have no idea what E0-E5 are for. The firmware contains no code to access
these registers. Maybe related to waveform debugging?

I think the ADC should be triggerred by either IFCLK or CTL2. 48/30 MHz
mode enables clock output on IFCLK and keeps CTL2 to 1. Lower modi switch
CTL2 in the wave form for every sample and disable clock output in
IFCONFIG. Are you sure CTL2 is not connected?

In stock firmware 24 MHz was broken and sampled with 48 MHz, while
disabling IFCLK and toggling CTL2 with 16 MHz (ok, only after patching the
right waveform). The result was that there were always 3 identical samples,
so CTL2 should have effects.

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#14 (comment)
.

[rpcope1]

Jochen, forgive me if I missing something, but how I see the external trigger being potentially used is that the timer for T0 is always set one bit away from overflow, and when the trigger line comes high, T0 will overflow and interrupt. On interrupt, the 8051 either stops the ADC sampling or disables the ADC's ability to write to the FIFO, either one occurring after enough cycles to get the time of triggering in the middle of data present in the FIFO; the ADC would not put data into the FIFO until a control command on USB comes in and restarts sampling, thus allowing the host to pull the data at the trigger time at some point later. This is obviously only useful if you have an external trigger source, but it would allow an external source to control the wave form that's sent to the host, kind of emulating the external trigger input on other scopes.

In looking through the datasheet, it's not totally clear if it's possible to stop the ADC's ability to write to the FIFO in a workable manner.

[jhoenicke]

You can abort the GPIF waveform, which stops writing to the FIFO until it is started again.
Also it is possible is to set the INTRDY flag and use that in the waveform to terminate more cleanly. One can also use the INTRDY flags as triggering signal to start sampling.

But this has to wait until we have our own firmware. I'm sick of patching the stock firmware.

[jhoenicke]

I just took a look myself and CTL2 and IFCLK both go to the two 0-Ohm resistors next to the CTL2 pin. I cannot see if they are then connected. At least IFCLK goes further to the ADC input clock. If CTL2 and IFCLK are directly connected I'm wondering if the design is sound. For lowspeed, IFCLK output is disabled, and CTL2 drives the clock, so this is okay. But for highspeed (30/48 MHz sampling) CTL2 is driven with CMOS 1 while IFCLK is driving the clock. In principle CTL2 is tri-statable, but the firmware never sets the TRICTL bit.

Update: CTL2 and IFCLK are connected. Should we tri-state CTL2 in our firmware, when we use IFCLK to drive the ADC?