-
Notifications
You must be signed in to change notification settings - Fork 0
/
stm32f4xx_rcc.h
1473 lines (1336 loc) · 70.3 KB
/
stm32f4xx_rcc.h
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/**
* @file stm32f405zgtx.h
* @author Samuel Martel
* @p https://www.github.com/smartel99
* @date 2020/09/06
* @brief Header file of RCC STM32 module.
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
#ifndef __STM32F405ZGTX_RCC_H__
#define __STM32F405ZGTX_RCC_H__
#include "stm32f405zgtx_def.h"
#include "stm32f405xx.h"
/** @addtogroup STM32
* @{
*/
namespace HAL
{
/** @defgroup RCC RCC
* @{
*/
namespace RstCtrlClk
{
/**
* @defgroup Exported_Constants Exported Constants
* @{
*/
/** @defgroup OscillatorType Oscillator Type
* @{
*/
enum class OscillatorType
{
None = 0x00,
HSE = 0x01,
HSi = 0x02,
LSE = 0x04,
LSI = 0x08
};
/** @} */
/** @defgroup HseConfig HSE Config
* @{
*/
enum class HseConfig
{
Off = 0x00,
On = RCC_CR_HSEON,
Bypass = ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
};
/** @} */
/** @defgroup LseConfig LSE Config
* @{
*/
enum class LseConfig
{
Off = 0x00,
On = RCC_BDCR_LSEON,
Bypass = ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
};
/** @} */
/** @defgroup HsiConfig HSI Config
* @{
*/
enum class HsiConfig
{
Off = 0x00,
On = 0x01,
};
/**
* @brief Default HSI calibration trimming value.
*/
constexpr uint32_t HsiCalibrationDefault = 0x10U;
/** @} */
/** @defgroup LsiConfig LSI Config
* @{
*/
enum class LsiConfig
{
Off = 0x00,
On = 0x01
};
/** @} */
/** @defgroup PllConfig PLL Config
* @{
*/
enum class PllConfig
{
None = 0x00,
Off = 0x01,
On = 0x02,
};
/** @} */
/** @defgroup PllPClockDivider PLLP Clock Divider
* @{
*/
enum class PllPClockDivider
{
Div2 = 0x00000002U,
Div4 = 0x00000004U,
Div6 = 0x00000006U,
Div8 = 0x00000008U
};
/** @} */
/** @defgroup PllClockSource PLL Clock Source
* @{
*/
enum class PllClockSource
{
HSI = RCC_PLLCFGR_PLLSRC_HSI,
HSE = RCC_PLLCFGR_PLLSRC_HSE,
};
/** @} */
/** @defgroup SystemClockType System Clock Type
* @{
*/
enum class SystemClockType
{
SYSCLK = 0x00000001U,
HCLK = 0x00000002U,
PCLK1 = 0x00000004U,
PCLK2 = 0x00000008U
};
/** @} */
/** @defgroup SystemClkSource System Clock Source
* @note The RCC_SYSCLKSOURCE_PLLRCLK parameter is available only for
* STM32F446xx devices.
* @{
*/
enum class SystemClkSource
{
HSI = RCC_CFGR_SW_HSI,
HSE = RCC_CFGR_SW_HSE,
PLLCLK = RCC_CFGR_SW_PLL,
PLLRCLK = ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))
};
/** @} */
/** @defgroup SystemClkSourceStatus System Clock Source Status
* @note The RCC_SYSCLKSOURCE_STATUS_PLLRCLK parameter is available only for
* STM32F446xx devices.
* @{
*/
enum class SystemClkSourceStatus
{
HSI = RCC_CFGR_SWS_HSI, /*!< HSI used as system clock */
HSE = RCC_CFGR_SWS_HSE, /*!< HSE used as system clock */
PLLCLK = RCC_CFGR_SWS_PLL, /*!< PLL used as system clock */
PLLRCLK = ((uint32_t)(RCC_CFGR_SWS_0 | RCC_CFGR_SWS_1)), /*!< PLLR used as system clock */
};
/** @} */
/** @defgroup SysclkDivider SYSCLK Clock Divider
* @{
*/
enum class SysclkDivider
{
Div1 = RCC_CFGR_HPRE_DIV1,
Div2 = RCC_CFGR_HPRE_DIV2,
Div4 = RCC_CFGR_HPRE_DIV4,
Div8 = RCC_CFGR_HPRE_DIV8,
Div16 = RCC_CFGR_HPRE_DIV16,
Div64 = RCC_CFGR_HPRE_DIV64,
Div128 = RCC_CFGR_HPRE_DIV128,
Div256 = RCC_CFGR_HPRE_DIV256,
Div512 = RCC_CFGR_HPRE_DIV512
};
/** @} */
/** @defgroup HclkDivider HCLK Clock Divider
* @{
*/
enum class HclkDivider
{
Div1 = RCC_CFGR_PPRE1_DIV1,
Div2 = RCC_CFGR_PPRE1_DIV2,
Div4 = RCC_CFGR_PPRE1_DIV4,
Div8 = RCC_CFGR_PPRE1_DIV8,
Div16 = RCC_CFGR_PPRE1_DIV16
};
/** @} */
/** @defgroup RtcClockSource RTC Clock Source
* @{
*/
enum class RtcClockSource
{
NO_CLK = 0x00000000U,
LSE = 0x00000100U,
LSI = 0x00000200U,
HSE_DIVX = 0x00000300U,
HSE_DIV2 = 0x00020300U,
HSE_DIV3 = 0x00030300U,
HSE_DIV4 = 0x00040300U,
HSE_DIV5 = 0x00050300U,
HSE_DIV6 = 0x00060300U,
HSE_DIV7 = 0x00070300U,
HSE_DIV8 = 0x00080300U,
HSE_DIV9 = 0x00090300U,
HSE_DIV10 = 0x000A0300U,
HSE_DIV11 = 0x000B0300U,
HSE_DIV12 = 0x000C0300U,
HSE_DIV13 = 0x000D0300U,
HSE_DIV14 = 0x000E0300U,
HSE_DIV15 = 0x000F0300U,
HSE_DIV16 = 0x00100300U,
HSE_DIV17 = 0x00110300U,
HSE_DIV18 = 0x00120300U,
HSE_DIV19 = 0x00130300U,
HSE_DIV20 = 0x00140300U,
HSE_DIV21 = 0x00150300U,
HSE_DIV22 = 0x00160300U,
HSE_DIV23 = 0x00170300U,
HSE_DIV24 = 0x00180300U,
HSE_DIV25 = 0x00190300U,
HSE_DIV26 = 0x001A0300U,
HSE_DIV27 = 0x001B0300U,
HSE_DIV28 = 0x001C0300U,
HSE_DIV29 = 0x001D0300U,
HSE_DIV30 = 0x001E0300U,
HSE_DIV31 = 0x001F0300U,
};
/** @} */
/** @defgroup McoIndex MCO Index
* @{
*/
enum class McoIndex
{
MCO1 = 0x00000000U,
MCO2 = 0x00000001U,
};
/** @} */
/** @defgroup Mco1ClockSource MCO1 Clock Source
* @{
*/
enum class Mco1ClockSource
{
HSI = 0x000000000U,
LSE = RCC_CFGR_MCO1_0,
HSE = RCC_CFGR_MCO1_1,
PLLCLK = RCC_CFGR_MCO1
};
/** @} */
/** @defgroup Mco2ClockSource MCO2 Clock Source
* @{
*/
enum class Mco2ClockSource
{
SYSCLK = 0x00000000U,
PLLI2SCLK = RCC_CFGR_MCO2_0,
HSE = RCC_CFGR_MCO2_1,
PLLCLK = RCC_CFGR_MCO2
};
/** @} */
/** @defgroup McoXClockPrescaller MCOx Clock Prescaller
* @{
*/
enum class McoXClockPrescaller
{
Div1 = 0x00000000U,
Div2 = RCC_CFGR_MCO1PRE_2,
Div3 = ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2),
Div4 = ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2),
};
/** @} */
/** @defgroup Interrupt Interrupts
* @{
*/
enum class Interrupt
{
LSIRdy = 0x01,
LSERdy = 0x02,
HSIRdy = 0x04,
HSERdy = 0x08,
PLLRdy = 0x10,
PLLI2SRdy = 0x20,
CSS = 0x80
};
/** @} */
/** @defgroup Flag Flags
* Elements values convention: 0XXYYYYYb
* - YYYYY : Flag position in the register
* - XX : Register index
* - 01 : CR register
* - 10 : BDCR register
* - 11 : CSR register
* @{
*/
enum class Flags
{
HSIRdy = 0x21,
HSERdy = 0x31,
PLLRdy = 0x39,
PLLI2SRdy = 0x3B,
LSERdy = 0x41,
LSIRdy = 0x61,
BORRST = 0x79,
PINRST = 0x7A,
PORRST = 0x7B,
SFTRST = 0x7C,
IWDGRST = 0x7D,
WWDGRST = 0x7E,
LPWRRST = 0x7F
};
/** @}
* Flag
*/
/** @}
* Exported_Constants
*/
/*****************************************************************************/
/* Exported Macros */
/*****************************************************************************/
/** @defgroup ExportedMacros RCC Exported Macros
* @{
*/
/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
* @brief Enable or disable the AHB1 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
* @{
*/
constexpr void GpioAClkEnable()
{
__IO uint32_t tmpreg = 0x00;
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);
// Delay after an RCC peripheral clock enabling.
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);
}
constexpr void GpioBClkEnable()
{
__IO uint32_t tmpreg = 0x00;
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);
// Delay after an RCC peripheral clock enabling.
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);
}
constexpr void GpioCClkEnable()
{
__IO uint32_t tmpreg = 0x00;
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
// Delay after an RCC peripheral clock enabling.
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
}
constexpr void GpioHClkEnable()
{
__IO uint32_t tmpreg = 0x00;
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);
// Delay after an RCC peripheral clock enabling.
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);
}
constexpr void Dma1ClkEnable()
{
__IO uint32_t tmpreg = 0x00;
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);
// Delay after an RCC peripheral clock enabling.
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);
}
constexpr void Dma2ClkEnable()
{
__IO uint32_t tmpreg = 0x00;
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);
// Delay after an RCC peripheral clock enabling.
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);
}
constexpr void GpioAClkDisable() { RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN); }
constexpr void GpioBClkDisable() { RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN); }
constexpr void GpioCClkDisable() { RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN); }
constexpr void GpioHClkDisable() { RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN); }
constexpr void Dma1ClkDisable() { RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN); }
constexpr void Dma2ClkDisable() { RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN); }
/** @}
* RCC_AHB1_Clock_Enable_Disable
*/
/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
* @brief Get the enable or disable status of the AHB1 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
* @{
*/
constexpr bool GpioAIsClkEnabled() { return ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != 0); }
constexpr bool GpioBIsClkEnabled() { return ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != 0); }
constexpr bool GpioCIsClkEnabled() { return ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != 0); }
constexpr bool GpioHIsClkEnabled() { return ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != 0); }
constexpr bool Dma1IsClkEnabled() { return ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) != 0); }
constexpr bool Dma2IsClkEnabled() { return ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != 0); }
constexpr bool GpioAIsClkDisabled() { return ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == 0); }
constexpr bool GpioBIsClkDisabled() { return ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == 0); }
constexpr bool GpioCIsClkDisabled() { return ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == 0); }
constexpr bool GpioHIsClkDisabled() { return ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == 0); }
constexpr bool Dma1IsClkDisabled() { return ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) == 0); }
constexpr bool Dma2IsClkDisabled() { return ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == 0); }
/** @}
* RCC_AHB1_Peripheral_Clock_Enable_Disable_Status
*/
/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
* @{
*/
constexpr void Tim5ClkEnable()
{
__IO uint32_t tmpreg = 0x00U;
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);
}
constexpr void WwdgClkEnable()
{
__IO uint32_t tmpreg = 0x00U;
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);
}
constexpr void Spi2ClkEnable()
{
__IO uint32_t tmpreg = 0x00U;
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);
}
constexpr void Usart2ClkEnable()
{
__IO uint32_t tmpreg = 0x00U;
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);
}
constexpr void I2c1ClkEnable()
{
__IO uint32_t tmpreg = 0x00U;
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);
}
constexpr void I2c2ClkEnable()
{
__IO uint32_t tmpreg = 0x00U;
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);
}
constexpr void PwrClkEnable()
{
__IO uint32_t tmpreg = 0x00U;
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);
}
constexpr void Tim5ClkDisable() { (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)); }
constexpr void WwdgClkDisable() { (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)); }
constexpr void Spi2ClkDisable() { (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)); }
constexpr void Usart2ClkDisable() { (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)); }
constexpr void I2c1ClkDisable() { (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)); }
constexpr void I2c2ClkDisable() { (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)); }
constexpr void PwrClkDisable() { (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)); }
/** @}
* RCC_APB1_Clock_Enable_Disable
*/
/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
* @brief Get the enable or disable status of the APB1 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
* @{
*/
constexpr bool Tim5IsClkEnabled() { return ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != 0); }
constexpr bool WwdgIsClkEnabled() { return ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != 0); }
constexpr bool Spi2IsClkEnabled() { return ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != 0); }
constexpr bool Usart2IsClkEnabled() { return ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != 0); }
constexpr bool I2c1IsClkEnabled() { return ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != 0); }
constexpr bool I2c2IsClkEnabled() { return ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != 0); }
constexpr bool PwrIsClkEnabled() { return ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != 0); }
constexpr bool Tim5IsClkDisabled() { return ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == 0); }
constexpr bool WwdgIsClkDisabled() { return ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == 0); }
constexpr bool Spi2IsClkDisabled() { return ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == 0); }
constexpr bool Usart2IsClkDisabled() { return ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == 0); }
constexpr bool I2c1IsClkDisabled() { return ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == 0); }
constexpr bool I2c2IsClkDisabled() { return ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == 0); }
constexpr bool PwrIsClkDisabled() { return ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == 0); }
/** @}
* RCC_APB1_Peripheral_Clock_Enable_Disable_Status
*/
/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
* @{
*/
constexpr void Tim1ClkEnable()
{
__IO uint32_t tmpreg = 0x00U;
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);
}
constexpr void Usart1ClkEnable()
{
__IO uint32_t tmpreg = 0x00U;
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);
}
constexpr void Usart6ClkEnable()
{
__IO uint32_t tmpreg = 0x00U;
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);
}
constexpr void Adc1ClkEnable()
{
__IO uint32_t tmpreg = 0x00U;
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);
}
constexpr void Spi1ClkEnable()
{
__IO uint32_t tmpreg = 0x00U;
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);
}
constexpr void SyscfgClkEnable()
{
__IO uint32_t tmpreg = 0x00U;
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);
}
constexpr void Tim9ClkEnable()
{
__IO uint32_t tmpreg = 0x00U;
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);
}
constexpr void Tim11ClkEnable()
{
__IO uint32_t tmpreg = 0x00U;
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);
}
constexpr void Tim1ClkDisable() { (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)); }
constexpr void Usart1ClkDisable() { (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)); }
constexpr void Usart6ClkDisable() { (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)); }
constexpr void Adc1ClkDisable() { (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)); }
constexpr void Spi1ClkDisable() { (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)); }
constexpr void SyscfgClkDisable() { (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)); }
constexpr void Tim9ClkDisable() { (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)); }
constexpr void Tim11ClkDisable() { (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)); }
/** @}
* RCC_APB2_Clock_Enable_Disable
*/
/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
* @brief Get the enable or disable status of the APB2 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
* @{
*/
constexpr bool Tim1IsClkEnabled() { return ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != 0); }
constexpr bool Usart1IsClkEnabled() { return ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != 0); }
constexpr bool Usart6IsClkEnabled() { return ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != 0); }
constexpr bool Adc1IsClkEnabled() { return ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != 0); }
constexpr bool Spi1IsClkEnabled() { return ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != 0); }
constexpr bool SyscfgIsClkEnabled() { return ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != 0); }
constexpr bool Tim9IsClkEnabled() { return ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != 0); }
constexpr bool Tim11IsClkEnabled() { return ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != 0); }
constexpr bool Tim1IsClkDisabled() { return ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == 0); }
constexpr bool Usart1IsClkDisabled() { return ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == 0); }
constexpr bool Usart6IsClkDisabled() { return ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == 0); }
constexpr bool Adc1IsClkDisabled() { return ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == 0); }
constexpr bool Spi1IsClkDisabled() { return ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == 0); }
constexpr bool SyscfgIsClkDisabled() { return ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == 0); }
constexpr bool Tim9IsClkDisabled() { return ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == 0); }
constexpr bool Tim11IsClkDisabled() { return ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == 0); }
/** @}
* RCC_APB2_Peripheral_Clock_Enable_Disable_Status
*/
/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset
* @brief Force or release AHB1 peripheral reset.
* @{
*/
constexpr void Ahb1ForceReset() { (RCC->AHB1RSTR = 0xFFFFFFFFU); }
constexpr void GpioAForceReset() { (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST)); }
constexpr void GpioBForceReset() { (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST)); }
constexpr void GpioCForceReset() { (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST)); }
constexpr void GpioHForceReset() { (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST)); }
constexpr void Dma1ForceReset() { (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST)); }
constexpr void Dma2ForceReset() { (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST)); }
constexpr void Ahb1ReleaseReset() { (RCC->AHB1RSTR = 0x00U); }
constexpr void GpioAReleaseReset() { (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST)); }
constexpr void GpioBReleaseReset() { (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST)); }
constexpr void GpioCReleaseReset() { (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST)); }
constexpr void GpioHReleaseReset() { (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST)); }
constexpr void Dma1ReleaseReset() { (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST)); }
constexpr void Dma2ReleaseReset() { (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST)); }
/** @}
* RCC_AHB1_Force_Release_Reset
*/
/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
* @brief Force or release APB1 peripheral reset.
* @{
*/
constexpr void Apb1ForceReset() { (RCC->APB1RSTR = 0xFFFFFFFFU); }
constexpr void Tim5ForceReset() { (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)); }
constexpr void WwdgForceReset() { (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)); }
constexpr void Spi1ForceReset() { (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)); }
constexpr void Usart2ForceReset() { (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)); }
constexpr void I2c1ForceReset() { (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)); }
constexpr void I2c2ForceReset() { (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)); }
constexpr void PwrForceReset() { (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)); }
constexpr void Apb1ReleaseReset() { (RCC->APB1RSTR = 0x00U); }
constexpr void Tim5ReleaseReset() { (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)); }
constexpr void WwdgReleaseReset() { (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)); }
constexpr void Spi1ReleaseReset() { (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)); }
constexpr void Usart2ReleaseReset() { (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)); }
constexpr void I2c1ReleaseReset() { (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)); }
constexpr void I2c2ReleaseReset() { (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)); }
constexpr void PwrReleaseReset() { (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)); }
/** @}
* RCC_APB1_Force_Release_Reset
*/
/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
* @brief Force or release APB2 peripheral reset.
* @{
*/
constexpr void Apb2ForceReset() { (RCC->APB2RSTR = 0xFFFFFFFFU); }
constexpr void Tim1ForceReset() { (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)); }
constexpr void Usart1ForceReset() { (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)); }
constexpr void Usart6ForceReset() { (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST)); }
constexpr void AdcForceReset() { (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST)); }
constexpr void Spi1ForceReset() { (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)); }
constexpr void SyscfgForceReset() { (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)); }
constexpr void Tim9ForceReset() { (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)); }
constexpr void Tim11ForceReset() { (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)); }
constexpr void Apb2ReleaseReset() { (RCC->APB2RSTR = 0x00U); }
constexpr void Tim1ReleaseReset() { (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)); }
constexpr void Usart1ReleaseReset() { (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)); }
constexpr void Usart6ReleaseReset() { (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST)); }
constexpr void AdcReleaseReset() { (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST)); }
constexpr void Spi1ReleaseReset() { (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)); }
constexpr void SyscfgReleaseReset() { (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)); }
constexpr void Tim9ReleaseReset() { (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)); }
constexpr void Tim11ReleaseReset() { (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)); }
/** @}
* RCC_APB2_Force_Release_Reset
*/
/** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
* @{
*/
constexpr void GpioAClkSleepEnable() { (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN)); }
constexpr void GpioBClkSleepEnable() { (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN)); }
constexpr void GpioCClkSleepEnable() { (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN)); }
constexpr void GpioHClkSleepEnable() { (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN)); }
constexpr void Dma1ClkSleepEnable() { (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)); }
constexpr void Dma2ClkSleepEnable() { (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)); }
constexpr void GpioAClkSleepDisable() { (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN)); }
constexpr void GpioBClkSleepDisable() { (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN)); }
constexpr void GpioCClkSleepDisable() { (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN)); }
constexpr void GpioHClkSleepDisable() { (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN)); }
constexpr void Dma1ClkSleepDisable() { (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN)); }
constexpr void Dma2ClkSleepDisable() { (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN)); }
/** @}
* RCC_AHB1_LowPower_Enable_Disable
*/
/** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
* @{
*/
constexpr void Tim5ClkSleepEnable() { (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN)); }
constexpr void WwdgClkSleepEnable() { (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN)); }
constexpr void Spi2ClkSleepEnable() { (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN)); }
constexpr void Usart2ClkSleepEnable() { (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN)); }
constexpr void I2c1ClkSleepEnable() { (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN)); }
constexpr void I2c2ClkSleepEnable() { (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN)); }
constexpr void PwrClkSleepEnable() { (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN)); }
constexpr void Tim5ClkSleepDisable() { (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN)); }
constexpr void WwdgClkSleepDisable() { (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN)); }
constexpr void Spi2ClkSleepDisable() { (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN)); }
constexpr void Usart2ClkSleepDisable() { (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN)); }
constexpr void I2c1ClkSleepDisable() { (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN)); }
constexpr void I2c2ClkSleepDisable() { (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN)); }
constexpr void PwrClkSleepDisable() { (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN)); }
/** @}
* RCC_APB1_LowPower_Enable_Disable
*/
/** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
* @{
*/
constexpr void Tim1ClkSleepEnable() { (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN)); }
constexpr void Usart1ClkSleepEnable() { (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN)); }
constexpr void Usart6ClkSleepEnable() { (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN)); }
constexpr void Adc1ClkSleepEnable() { (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN)); }
constexpr void Spi1ClkSleepEnable() { (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN)); }
constexpr void SyscfgClkSleepEnable() { (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN)); }
constexpr void Tim9ClkSleepEnable() { (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN)); }
constexpr void Tim11ClkSleepEnable() { (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN)); }
constexpr void Tim1ClkSleepDisable() { (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN)); }
constexpr void Usart1ClkSleepDisable() { (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN)); }
constexpr void Usart6ClkSleepDisable() { (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN)); }
constexpr void Adc1ClkSleepDisable() { (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN)); }
constexpr void Spi1ClkSleepDisable() { (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN)); }
constexpr void SyscfgClkSleepDisable() { (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN)); }
constexpr void Tim9ClkSleepDisable() { (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN)); }
constexpr void Tim11ClkSleepDisable() { (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN)); }
/** @}
* RCC_APB2_LowPower_Enable_Disable
*/
/** @defgroup RCC_HSI_Configuration HSI Configuration
* @{
*/
/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
* It is used (enabled by hardware) as system clock source after startup
* from Reset, wake-up from STOP and STANDBY mode, or in case of failure
* of the HSE used directly or indirectly as system clock (if the Clock
* Security System CSS is enabled).
* @note HSI can not be stopped if it is used as system clock source. In this case,
* you have to select another source of the system clock then stop the HSI.
* @note After enabling the HSI, the application software should wait on HSIRDY
* flag to be set indicating that HSI clock is stable and can be used as
* system clock source.
* This parameter can be: ENABLE or DISABLE.
* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
* clock cycles.
*/
constexpr void HsiEnable() { *(__IO uint32_t *)RCC_CR_HSION_BB = ~0U; }
constexpr void HsiDisable() { *(__IO uint32_t *)RCC_CR_HSION_BB = 0U; }
/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
* @note The calibration is used to compensate for the variations in voltage
* and temperature that influence the frequency of the internal HSI RC.
* @param __HSICalibrationValue__ specifies the calibration trimming value.
* (default is RCC_HSICALIBRATION_DEFAULT).
* This parameter must be a number between 0 and 0x1F.
*/
template <typename T = uint32_t>
constexpr void HsiCalibrationValueAdjust(T value) { (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(value) << RCC_CR_HSITRIM_Pos)); }
/** @}
* RCC_HSI_Configuration
*/
/** @defgroup RCC_LSI_Configuration LSI Configuration
* @{
*/
/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
* @note After enabling the LSI, the application software should wait on
* LSIRDY flag to be set indicating that LSI clock is stable and can
* be used to clock the IWDG and/or the RTC.
* @note LSI can not be disabled if the IWDG is running.
* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
* clock cycles.
*/
constexpr void LsiEnable() { *(__IO uint32_t *)RCC_CSR_LSION_BB = ~0U; }
constexpr void LsiDisable() { *(__IO uint32_t *)RCC_CSR_LSION_BB = 0U; }
/** @}
* RCC_LSI_Configuration
*/
/** @defgroup RCC_HSE_Configuration HSE Configuration
* @{
*/
/**
* @brief Macro to configure the External High Speed oscillator (HSE).
* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
* User should request a transition to HSE Off first and then HSE On or HSE Bypass.
* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
* software should wait on HSERDY flag to be set indicating that HSE clock
* is stable and can be used to clock the PLL and/or system clock.
* @note HSE state can not be changed if it is used directly or through the
* PLL as system clock. In this case, you have to select another source
* of the system clock then change the HSE state (ex. disable it).
* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
* @note This function reset the CSSON bit, so if the clock security system(CSS)
* was previously enabled you have to enable it again after calling this
* function.
* @param __STATE__ specifies the new state of the HSE.
* This parameter can be one of the following values:
* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
* 6 HSE oscillator clock cycles.
* @arg RCC_HSE_ON: turn ON the HSE oscillator.
* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
*/
constexpr void ConfigHse(HseConfig state)
{
if (state == HseConfig::On)
{
SET_BIT(RCC->CR, RCC_CR_HSEON);
}
else if (state == HseConfig::Bypass)
{
SET_BIT(RCC->CR, RCC_CR_HSEBYP);
SET_BIT(RCC->CR, RCC_CR_HSEON);
}
else
{
CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
}
}
/** @}
* RCC_HSE_Configuration
*/
/** @defgroup RCC_LSE_Configuration LSE Configuration
* @{
*/
/**
* @brief Macro to configure the External Low Speed oscillator (LSE).
* @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
* User should request a transition to LSE Off first and then LSE On or LSE Bypass.
* @note As the LSE is in the Backup domain and write access is denied to
* this domain after reset, you have to enable write access using
* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
* (to be done once after reset).
* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
* software should wait on LSERDY flag to be set indicating that LSE clock
* is stable and can be used to clock the RTC.
* @param __STATE__ specifies the new state of the LSE.
* This parameter can be one of the following values:
* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
* 6 LSE oscillator clock cycles.
* @arg RCC_LSE_ON: turn ON the LSE oscillator.
* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
*/
constexpr void ConfigLse(LseConfig state)
{
if (state == LseConfig::On)
{
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
}
else if (state == LseConfig::Bypass)
{
SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
}
else
{
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
}
}
/** @}
* RCC_LSE_Configuration
*/
/** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
* @{
*/
/** @brief Macros to enable or disable the RTC clock.
* @note These macros must be used only after the RTC clock source was selected.
*/
constexpr void RtcEnable() { *(__IO uint32_t *)RCC_BDCR_RTCEN_BB = ~0U; }
constexpr void RtcDisable() { *(__IO uint32_t *)RCC_BDCR_RTCEN_BB = 0; }
/** @brief Macros to configure the RTC clock (RTCCLK).
* @note As the RTC clock configuration bits are in the Backup domain and write
* access is denied to this domain after reset, you have to enable write
* access using the Power Backup Access macro before to configure
* the RTC clock source (to be done once after reset).
* @note Once the RTC clock is configured it can't be changed unless the
* Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
* a Power On Reset (POR).
* @param __RTCCLKSource__ specifies the RTC clock source.
* This parameter can be one of the following values:
@arg @ref RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock.
* @arg @ref RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
* @arg @ref RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
* @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected
* as RTC clock, where x:[2,31]
* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
* work in STOP and STANDBY modes, and can be used as wake-up source.
* However, when the HSE clock is used as RTC clock source, the RTC
* cannot be used in STOP and STANDBY modes.
* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
* RTC clock source).
*/
constexpr void SetRtcClkPrescaler(RtcClockSource clkSrc)
{
(((uint32_t)clkSrc & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, (((uint32_t)(clkSrc)) & 0xFFFFCFFU))
: CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE);
}
constexpr void ConfigRtc(RtcClockSource clkSrc)
{
SetRtcClkPrescaler(clkSrc);
RCC->BDCR |= ((uint32_t)clkSrc & 0x00000FFFU);
}
/** @brief Macro to get the RTC clock source.
* @retval The clock source can be one of the following values:
* @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
* @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
*/
constexpr RtcClockSource GetRtcClkSource() { return (RtcClockSource)READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); }
/**
* @brief Get the RTC and HSE clock divider (RTCPRE).
* @retval Returned value can be one of the following values: