Soutys8 is an 8-bit softprocessor (hereinafter referred to as the processor) written in VHDL (Very High Speed Integrated Circuit Hardware Description Language) created for didactic purposes. It is mainly characterized by:
- clear block structure,
- executing all instructions in one clock cycle,
- scalability that allows it to be implemented in almost any FPGA system.
Soutys8 block diagram
The architecture of the Soutys8 processor was based on the Harvard architecture, which is characterized by the separation of the data memory from the instruction memory. In addition, we can distinguish three main communication buses between the processor blocks. The first of them, the internal bus, is responsible for e.g. for data transfer between the arithmetic and logic unit and general purpose registers. The second of them, the memory bus, is responsible for e.g. for addressing data memory or I/O registers and is controlled by the instruction decoder. The last of them, the control bus, is responsible for controlling the processes of data writing and reading and for calculating the next value of the instruction counter in the case of execution of conditional and absolute jump instructions.
Soutys8 data memory diagram
The instruction set of the Soutys8 processor consists of 49 16-bit or 32-bit instructions compatible with the instruction set of AVR microcontrollers (the full list of implemented instructions is included in the Instruction_decoder.vhd file). Additional compatibility with AVR microcontrollers is the mapping of the data memory map and its division into general purpose registers, input/output space and main memory. This combination allows you to program the processor memory with binary files (.hex extension) created directly by development tools designed for programming AVR family processors in assembler language.
Existing file hierarchy has been created using Active-HDL software (Windows only).
The src/ directory contains all the source files (.vhd extension) and testbenches. The compile/ directory contains .vhd files generated by the Active-HDL from the block diagrams.