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[CODE SHARING] Insertions of custom LLVM IR and AMDGCN codes to triton #610

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[CODE SHARING] Insertions of custom LLVM IR and AMDGCN codes to triton #610

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Commits on Jun 25, 2024

  1. [AMD-Pipeliner] Transition stream-pipeline to new SW pipelining infra… 

    …structure

    - Copied scheduler from MatmulLoopPipeline (much could be consolidated)
    - Enable register buffering (even though may increases register pressure)
    - Enable num_stages=2+, including multi-buffering, and make `2` the default
    - updated tutorial for new tuning default
    - added lit	tests
    @sjw36
    sjw36 committed Jun 25, 2024
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  2. [AMD-Reorder] Move tt.loads as early as possible 

    - Also move independent(from loop-carried buffer) `triton_gpu.local_store` as early as possible
    @sjw36
    sjw36 committed Jun 25, 2024
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  3. * consolidated/fixed stream-pipeliner tests

    @sjw36
    sjw36 committed Jun 25, 2024
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  4. * updated test

    @sjw36
    sjw36 committed Jun 25, 2024
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  5. * Find insertion point for loads/local_stores as early as possible 

    - check for last atomic (sync?)
- also check for other accesses to the source
    @sjw36
    sjw36 committed Jun 25, 2024
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  6. * Reorder with BFS to keep relative order.

    @sjw36
    sjw36 committed Jun 25, 2024
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  7. * fixed pruning

    @sjw36
    sjw36 committed Jun 25, 2024
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Commits on Jun 26, 2024

  1. * updated test

    @sjw36
    sjw36 committed Jun 26, 2024
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Commits on Jun 27, 2024

  1. * invert order of loads and local_stores

    @sjw36
    sjw36 committed Jun 27, 2024
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Commits on Jul 9, 2024

  1. Added insertions of LLVM-IR and AMDGCN codes vie env. vars

    @ravil-mobile
    ravil-mobile committed Jul 9, 2024
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