Apache TVM v0.10.0

Introduction

The TVM community has worked since the v0.9 release to deliver the following new exciting improvments!

• Metaschedule
  • Software pipelining and padding for irregular shapes for auto tensorization
  • Stabilized and polished user-interfaces (e.g. database changes, tune_relay)
  • A new MLP-based cost model
• TIR
  • New schedule primitive for PadEinsum
  • A new TIR node: DeclBuffer
  • INT8 Intrinsics for TensorCores for CUDA!
• microTVM
  • Improved schedule primitives for ARM v8-m ISA

And many other general improvements to code quality, TVMScript, and more! Please visit the full listing of commits for a complete view: v0.9.0...v0.10.0rc0.

RFCs

These RFCs have been merged in apache/tvm-rfcs since the last release.

• Issue Triage Workflow RFC (#93) (3345cc1)

• [RFC] Add Commit Message Guideline (#88) (e8a2d8b)

• Add Target Features RFC (#78) (1ab898d)

• [RFC] TVMScript Metaprogramming (#79) (ffbf686)

• Add Target Pre-processing RFC (#71) (78423c5)

• [RFC] Name mangling in IRModules (#84) (831d702)

• Asynchronous stage in software pipeline (#80) (aecb219)

• [RFC] Buffer Layout Padding (#77) (ca695fe)

• [RFC] Create LLVM scope class for use with LLVM libraries (#83) (22d1d11)

What's Changed

Please visit the full listing of commits for a complete view: v0.9.0...v0.10.0rc0.

Note that this list is not comprehensive of all PRs and discussions since v0.9. A non-truncated summary can be found here: #12979

TIR

• #12720 - [TIR] Implement API for padded layout transformations
• #12797 - [TIR] Construct the inverse in SuggestIndexMap
• #12827 - [TIR] Support pattern matching argmax/argmin generated by TOPI
• #12750 - [TIR, Schedule] Add schedule primitive PadEinsum
• #11639 - [TIR][Meta-Schedule] Tuple-reduction scheduling support
• #12515 - [TIR][Arith] Add more strict checking in imm construction and folding.
• #12717 - [TIR, Schedule] Check consumer in-bound and covered in reverse_compute_inline
• #12652 - [TIR] Handle axis_separators during FlattenBuffer
• #12623 - [TIR] Expose MMA-related PTX builtins
• #12607 - [TIR][Schedule] enhance compute_at and reverse_compute_at primitive to choose possible position
  ...