update pitch

gateware/tests/test_dsp.py

@@ -49,32 +49,32 @@ def test_pitch(self):
         pitch_shift = dsp.PitchShift(delayln=delay_line, xfade=32)
         m.submodules += [delay_line, pitch_shift]
 
-        def testbench():
-            yield Tick()
-            yield Tick()
+        async def testbench(ctx):
+            await ctx.tick()
+            await ctx.tick()
             for n in range(0, 1000):
                 x = fixed.Const(0.8*math.sin(n*0.1), shape=ASQ)
-                yield delay_line.sw.valid.eq(1)
-                yield delay_line.sw.payload.eq(x)
-                yield Tick()
-                yield delay_line.sw.valid.eq(0)
-                yield Tick()
-                yield Tick()
-                yield pitch_shift.i.payload.pitch.eq(
+                ctx.set(delay_line.sw.valid, 1)
+                ctx.set(delay_line.sw.payload, x)
+                await ctx.tick()
+                ctx.set(delay_line.sw.valid, 0)
+                await ctx.tick()
+                await ctx.tick()
+                ctx.set(pitch_shift.i.payload.pitch, 
                     fixed.Const(-0.8, shape=pitch_shift.dtype))
-                yield pitch_shift.i.payload.grain_sz.eq(
+                ctx.set(pitch_shift.i.payload.grain_sz, 
                     delay_line.max_delay//2)
-                yield pitch_shift.o.ready.eq(1)
-                yield pitch_shift.i.valid.eq(1)
-                yield Tick()
-                yield pitch_shift.i.valid.eq(0)
-                yield Tick()
-                while (yield pitch_shift.i.ready) != 1:
-                    yield Tick()
+                ctx.set(pitch_shift.o.ready, 1)
+                ctx.set(pitch_shift.i.valid, 1)
+                await ctx.tick()
+                ctx.set(pitch_shift.i.valid, 0)
+                await ctx.tick()
+                while ctx.get(pitch_shift.i.ready) != 1:
+                    await ctx.tick()
 
         sim = Simulator(m)
         sim.add_clock(1e-6)
-        sim.add_process(testbench)
+        sim.add_testbench(testbench)
         with sim.write_vcd(vcd_file=open("test_pitch.vcd", "w")):
             sim.run()