test_raster/test_midi: add some coverage

gateware/src/tiliqua/raster.py

@@ -42,8 +42,8 @@ def __init__(self, *, fb_base, bus_master, fb_size,
         self.fb_bytes_per_pixel = fb_bytes_per_pixel
 
         # Tweakables
-        self.holdoff = Signal(16, reset=holdoff_default)
-        self.decay   = Signal(4, reset=1)
+        self.holdoff = Signal(16, init=holdoff_default)
+        self.decay   = Signal(4, init=1)
 
         # We are a DMA master
         self.bus = wishbone.Interface(addr_width=bus_master.addr_width, data_width=32, granularity=8,
@@ -53,11 +53,11 @@ def __init__(self, *, fb_base, bus_master, fb_size,
         self.fifo = SyncFIFO(width=32, depth=fifo_depth)
 
         # Current addresses in the framebuffer (read and write sides)
-        self.dma_addr_in = Signal(32, reset=0)
+        self.dma_addr_in = Signal(32, init=0)
         self.dma_addr_out = Signal(32)
 
         # Kick to start this core.
-        self.enable = Signal(1, reset=0)
+        self.enable = Signal(1, init=0)
 
     def elaborate(self, platform) -> Module:
         m = Module()
@@ -212,18 +212,18 @@ def __init__(self, *, fb_base, bus_master, fb_size, fb_bytes_per_pixel=1, fs=192
         self.sample_p = Signal(signed(16)) # intensity modulation TODO
         self.sample_c = Signal(signed(16)) # color modulation DONE
 
-        self.hue       = Signal(4, reset=default_hue);
-        self.intensity = Signal(4, reset=8);
-        self.scale_x   = Signal(4, reset=6);
-        self.scale_y   = Signal(4, reset=6);
-        self.x_offset  = Signal(signed(16), reset=default_x)
-        self.y_offset  = Signal(signed(16), reset=default_y)
+        self.hue       = Signal(4, init=default_hue);
+        self.intensity = Signal(4, init=8);
+        self.scale_x   = Signal(4, init=6);
+        self.scale_y   = Signal(4, init=6);
+        self.x_offset  = Signal(signed(16), init=default_x)
+        self.y_offset  = Signal(signed(16), init=default_y)
 
         self.px_read = Signal(32)
         self.px_sum = Signal(16)
 
         # Kick this to start the core
-        self.enable = Signal(1, reset=0)
+        self.enable = Signal(1, init=0)
 
         super().__init__()
 

gateware/src/tiliqua/scope.py

@@ -1,6 +1,9 @@
 # Copyright (c) 2024 Seb Holzapfel, apfelaudio UG <[email protected]>
 #
 # SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+Multi-channel oscilloscope and vectorscope SoC peripherals.
+"""
 
 from amaranth                                    import *
 from amaranth.lib                                import wiring, data, stream

gateware/tests/test_dsp.py

@@ -1,3 +1,7 @@
+# Copyright (c) 2024 Seb Holzapfel, apfelaudio UG <[email protected]>
+#
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+
 import sys
 import unittest
 

gateware/tests/test_i2c.py

@@ -1,3 +1,7 @@
+# Copyright (c) 2024 Seb Holzapfel, apfelaudio UG <[email protected]>
+#
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+
 import unittest
 
 from amaranth              import *

gateware/tests/test_midi.py

@@ -0,0 +1,41 @@
+# Copyright (c) 2024 Seb Holzapfel, apfelaudio UG <[email protected]>
+#
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+
+import math
+import sys
+import unittest
+
+from amaranth              import *
+from amaranth.sim          import *
+from amaranth.lib          import wiring
+from tiliqua               import midi, test_util
+
+from amaranth_soc          import csr
+from amaranth_soc.csr      import wishbone
+
+class MidiTests(unittest.TestCase):
+
+    def test_midi(self):
+
+        dut = midi.MidiDecode()
+
+        async def testbench(ctx):
+            ctx.set(dut.i.valid,   1)
+            ctx.set(dut.i.payload, 0x92)
+            await ctx.tick()
+            ctx.set(dut.i.payload, 0x48)
+            await ctx.tick()
+            ctx.set(dut.i.payload, 0x96)
+            await ctx.tick()
+            p = ctx.get(dut.o.payload)
+            self.assertEqual(p.midi_type, midi.MessageType.NOTE_ON)
+            self.assertEqual(p.midi_channel, 2)
+            self.assertEqual(p.midi_payload.note_on.note, 0x48)
+            self.assertEqual(p.midi_payload.note_on.velocity, 0x96)
+
+        sim = Simulator(dut)
+        sim.add_clock(1e-6)
+        sim.add_testbench(testbench)
+        with sim.write_vcd(vcd_file=open("test_midi.vcd", "w")):
+            sim.run()

gateware/tests/test_raster.py

@@ -0,0 +1,94 @@
+# Copyright (c) 2024 Seb Holzapfel, apfelaudio UG <[email protected]>
+#
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+
+import math
+import sys
+import unittest
+
+from amaranth              import *
+from amaranth.sim          import *
+from amaranth.lib          import wiring
+from tiliqua               import raster, test_util, eurorack_pmod
+
+from amaranth_soc          import csr
+from amaranth_soc.csr      import wishbone
+
+from amaranth_future       import fixed
+
+class RasterTests(unittest.TestCase):
+
+    def test_persist(self):
+
+        class FakeBusMaster:
+            addr_width = 30
+
+        dut = raster.Persistance(
+            fb_base=0x0,
+            bus_master=FakeBusMaster(),
+            fb_size=(1280, 720)
+        )
+
+        async def testbench(ctx):
+            ctx.set(dut.enable, 1)
+            # Simulate N burst accesses
+            for _ in range(4):
+                while not ctx.get(dut.bus.stb):
+                    await ctx.tick()
+                # Simulate acks delayed from stb
+                await ctx.tick().repeat(8)
+                ctx.set(dut.bus.ack, 1)
+                while ctx.get(dut.bus.stb):
+                    # for all burst accesses, simulate full intensity.
+                    ctx.set(dut.bus.dat_r, 0xffffffff)
+                    if ctx.get(dut.bus.we):
+                        # for all burst reads, verify intensity of every
+                        # pixel is reduced as expected
+                        self.assertEqual(ctx.get(dut.bus.dat_w),
+                                         0xefefefef)
+                    await ctx.tick()
+                ctx.set(dut.bus.ack, 0)
+
+        sim = Simulator(dut)
+        sim.add_clock(1e-6)
+        sim.add_testbench(testbench)
+        with sim.write_vcd(vcd_file=open("test_persist.vcd", "w")):
+            sim.run()
+
+    def test_stroke(self):
+
+        class FakeBusMaster:
+            addr_width = 30
+
+        dut = raster.Stroke(
+            fb_base=0x0,
+            bus_master=FakeBusMaster(),
+            fb_size=(1280, 720)
+        )
+
+        async def stimulus(ctx):
+            for n in range(0, sys.maxsize):
+                ctx.set(dut.i.valid, 1)
+                ctx.set(dut.i.payload, [0, 0, 0, 0])
+                await ctx.tick()
+                ctx.set(dut.i.valid, 0)
+                await ctx.tick().repeat(128)
+
+        async def testbench(ctx):
+            ctx.set(dut.enable, 1)
+            # Simulate some acks delayed from stb
+            for _ in range(16):
+                while not ctx.get(dut.bus.stb):
+                    await ctx.tick()
+                await ctx.tick().repeat(8)
+                ctx.set(dut.bus.ack, 1)
+                await ctx.tick()
+                ctx.set(dut.bus.ack, 0)
+                await ctx.tick()
+
+        sim = Simulator(dut)
+        sim.add_clock(1e-6)
+        sim.add_testbench(testbench)
+        sim.add_process(stimulus)
+        with sim.write_vcd(vcd_file=open("test_stroke.vcd", "w")):
+            sim.run()