further reduce latency

apfelaudio · Nov 10, 2024 · de98b2f · de98b2f
1 parent 5eb8fe2
commit de98b2f
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Showing 2 changed files with 4 additions and 4 deletions.
diff --git a/gateware/src/top/macro_osc/fw/src/main.rs b/gateware/src/top/macro_osc/fw/src/main.rs
@@ -28,9 +28,9 @@ use amaranth_soc_isr::return_as_is;
 
 use mi_plaits_dsp::dsp::voice::{Modulations, Patch, Voice};
 
-const BLOCK_SIZE: usize = 128;
+const BLOCK_SIZE: usize = 64;
 
-pub const TIMER0_ISR_PERIOD_MS: u32 = 10;
+pub const TIMER0_ISR_PERIOD_MS: u32 = 5;
 
 tiliqua_hal::impl_dma_display!(DMADisplay, H_ACTIVE, V_ACTIVE, VIDEO_ROTATE_90);
 
@@ -144,7 +144,7 @@ fn timer0_handler(app: &Mutex<RefCell<App>>) {
         modulations.morph = ((pmod.sample_i3().read().bits() as i16) as f32) / 16384.0f32;
 
         let mut n_attempts = 0;
-        while (audio_fifo.fifo_len().read().bits() as usize) < 512 - BLOCK_SIZE {
+        while (audio_fifo.fifo_len().read().bits() as usize) < 256 - BLOCK_SIZE {
             n_attempts += 1;
             if n_attempts > 10 {
                 // TODO set underrun flag

diff --git a/gateware/src/top/macro_osc/top.py b/gateware/src/top/macro_osc/top.py
@@ -39,7 +39,7 @@ class AudioFIFOPeripheral(wiring.Component):
     class FifoLenReg(csr.Register, access="r"):
         fifo_len: csr.Field(csr.action.R, unsigned(16))
 
-    def __init__(self, fifo_sz=4*4, fifo_data_width=32, granularity=8, elastic_sz=512):
+    def __init__(self, fifo_sz=4*4, fifo_data_width=32, granularity=8, elastic_sz=256):
         regs = csr.Builder(addr_width=6, data_width=8)
 
         self._fifo0 = fifo.SyncFIFOBuffered(