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Add support for LDR/STR T3 with imm12 immediate #3

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Add support for LDR/STR T3 with imm12 immediate #3

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44 changes: 44 additions & 0 deletions libsim/src/cpu.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -309,10 +309,18 @@ Step_status Cpu::step(void)
{
this->execute_op32_str_imm(ins16, ins16_b);
}
else if (TEST_INS32(OP32_STR_IMM12))
{
this->execute_op32_str_imm12(ins16, ins16_b);
}
else if (TEST_INS32(OP32_LDR_IMM))
{
this->execute_op32_ldr_imm(ins16, ins16_b);
}
else if (TEST_INS32(OP32_LDR_IMM12))
{
this->execute_op32_ldr_imm12(ins16, ins16_b);
}
else if (TEST_INS32(OP32_LDRB_IMM))
{
this->execute_op32_ldrb_imm(ins16, ins16_b);
Expand Down Expand Up @@ -1969,6 +1977,23 @@ void Cpu::execute_op32_branch_misc(uint16_t ins16, uint16_t ins16_b)
}


void Cpu::execute_op32_str_imm12(uint16_t ins16, uint16_t ins16_b)
{
/* STR(immediate) A6.7.119/T3 */
CPU_LOG_TRACE("OP32_STR_IMM12\n");
this->pc += 4;
unsigned int rn = GET_FIELD(ins16, 0, 4);
unsigned int rt = GET_FIELD(ins16_b, 12, 4);
unsigned int imm12 = GET_FIELD(ins16_b, 0, 12);
uint32_t current_rn = this->regs[rn].read();
this->reg_a.write(current_rn);
uint32_t d_addr = current_rn + imm12;
uint32_t current_rt = this->regs[rt].read();
this->reg_b.write(current_rt);
this->ram.write32(d_addr, current_rt);
}


void Cpu::execute_op32_str_imm(uint16_t ins16, uint16_t ins16_b)
{
/* STR(immediate) A6.7.119/T4 */
Expand Down Expand Up @@ -2041,6 +2066,25 @@ void Cpu::execute_op32_ldr_imm(uint16_t ins16, uint16_t ins16_b)
this->regs[rt].write(data);
}


void Cpu::execute_op32_ldr_imm12(uint16_t ins16, uint16_t ins16_b)
{
/* LDR(immediate) A6.7.42/T3 */
CPU_LOG_TRACE("OP32_LDR_IMM12\n");
this->pc += 4;
unsigned int rn = GET_FIELD(ins16, 0, 4);
unsigned int rt = GET_FIELD(ins16_b, 12, 4);
unsigned int imm12 = GET_FIELD(ins16_b, 0, 12);
uint32_t current_rn = this->regs[rn].read();
this->reg_a.write(current_rn);
uint32_t d_addr = current_rn + imm12;
uint32_t data = this->ram.read32(d_addr);
uint32_t current_rt = this->regs[rt].read();
this->reg_b.write(current_rt);
this->regs[rt].write(data);
}


void Cpu::execute_op32_ldrb_imm(uint16_t ins16, uint16_t ins16_b)
{
/* LDRB (imm) A6.7.45/T2 */
Expand Down
2 changes: 2 additions & 0 deletions libsim/src/cpu.h
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Expand Up @@ -128,7 +128,9 @@ class Cpu
void execute_op32_data_reg(uint16_t ins16, uint16_t ins16_b);
void execute_op32_branch_misc(uint16_t ins16, uint16_t ins16_b);
void execute_op32_str_imm(uint16_t ins16, uint16_t ins16_b);
void execute_op32_str_imm12(uint16_t ins16, uint16_t ins16_b);
void execute_op32_ldr_imm(uint16_t ins16, uint16_t ins16_b);
void execute_op32_ldr_imm12(uint16_t ins16, uint16_t ins16_b);
void execute_op32_ldrb_imm(uint16_t ins16, uint16_t ins16_b);
void execute_op32_ldrb_imm_alt(uint16_t ins16, uint16_t ins16_b);
void execute_op32_ldrb_reg(uint16_t ins16, uint16_t ins16_b);
Expand Down
6 changes: 6 additions & 0 deletions libsim/src/opcodes.h
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Expand Up @@ -150,9 +150,15 @@
#define OP32_STR_IMM_MASK 0xfff00800U
#define OP32_STR_IMM_VAL 0xf8400800U

#define OP32_STR_IMM12_MASK 0xfff00000U
#define OP32_STR_IMM12_VAL 0xf8c00000U

#define OP32_LDR_IMM_MASK 0xfff00800U
#define OP32_LDR_IMM_VAL 0xf8500800U

#define OP32_LDR_IMM12_MASK 0xfff00000U
#define OP32_LDR_IMM12_VAL 0xf8d00000U

#define OP32_LDRB_IMM_MASK 0xfff00000U
#define OP32_LDRB_IMM_VAL 0xf8900000U

Expand Down