riscv: dts: starfive: add assigned-clock* to limit frquency

mainline inclusion from mainline-v6.7-rc1 In JH7110 SoC, we need to go by-pass mode, so we need add the assigned-clock* properties to limit clock frquency. Signed-off-by: William Qiu <[email protected]> Reviewed-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]> (cherry picked from commit af57113)
deepin-community · Sep 4, 2024 · 963eade · 963eade
1 parent c43f4ed
commit 963eade
Showing 1 changed file with 4 additions and 0 deletions.
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -249,6 +249,8 @@
 
 &mmc0 {
 	max-frequency = <100000000>;
+	assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
+	assigned-clock-rates = <50000000>;
 	bus-width = <8>;
 	cap-mmc-highspeed;
 	mmc-ddr-1_8v;
@@ -265,6 +267,8 @@
 
 &mmc1 {
 	max-frequency = <100000000>;
+	assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
+	assigned-clock-rates = <50000000>;
 	bus-width = <4>;
 	no-sdio;
 	no-mmc;