Fixes out of memory error with larger RTL blocks

The autoname pass seems to cause issues with larger rtl blocks. Since the autoname pass really only assits with net names, and to be honest not that much. We can just remove it for now. Signed-off-by: Ethan Mahintorabi <[email protected]>
hdl · Jul 25, 2024 · 60b5cda · 60b5cda
1 parent 72906cc
commit 60b5cda
Showing 1 changed file with 0 additions and 3 deletions.
diff --git a/synthesis/synth.tcl b/synthesis/synth.tcl
@@ -61,7 +61,6 @@ yosys delete {*/t:$print}
 # useful names. At this stage it is mainly flipflops created by the `proc`
 # pass.
 yosys opt_clean -purge
-yosys autoname
 
 yosys synth -top $top
 
@@ -70,7 +69,6 @@ yosys synth -top $top
 # This should be done before techmapping where things can be converted
 # dramatically and having useful names is helpful for debugging.
 yosys opt_clean -purge
-yosys autoname
 
 # Technology mapping of adders
 if {[info exists ::env(ADDER_MAPPING)] && [file isfile $::env(ADDER_MAPPING)]} {
@@ -115,7 +113,6 @@ if {[info exists ::env(TIEHI_CELL_AND_PORT)] && [info exists ::env(TIELO_CELL_AN
 # useful names. At this stage it is anything generated by the techmapping
 # passes.
 yosys opt_clean -purge
-yosys autoname
 
 # write synthesized design
 set output $::env(OUTPUT)