Superscalar Branch Predictor
<<<<<<< Updated upstream
gold: The branch predictor model raw/direct model bench & test
oldest superscalar fetch?
Yeh, Tse-Yu, Deborah T. Marr, and Yale N. Patt. "Increasing the instruction fetch rate via multiple branch prediction and a branch address cache." Proceedings of the 7th International Conference on Supercomputing. 1993.
Do multiple predictors (one per fetch) and then have some other to combine:
G. H. Loh, "A simple divide-and-conquer approach for neural-class branch prediction," 14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05), St. Louis, MO, USA, 2005, pp. 243-254, doi: 10.1109/PACT.2005.6.
Dual port: to go ahead 2 branches (used by fabscalar)
Seznec, André, et al. "Multiple-block ahead branch predictors." ACM SIGPLAN Notices 31.9 (1996): 116-127.
Stashed changes