Fix misaligned jump target exception handling

[teobiton]

As per the specifications, instruction-address-misaligned exceptions should be reported for instructions that are not 16-bit aligned if the C extension is supported, and for instructions that are not 32-bit aligned if not.

[github-actions]

❌ failed run, report available here.

[github-actions]

❌ failed run, report available here.

[github-actions]

❌ failed run, report available here.

[zarubaf]

You shouldn't be able to trigger this exception if RVC is enabled. Since the LSB is cleared:

2.5.1. Unconditional Jumps

The indirect jump instruction JALR (jump and link register) uses the I-type encoding. The target
address is obtained by adding the sign-extended 12-bit I-immediate to the register rs1, then setting the least-significant bit of the result to zero.

[teobiton]

Yes, I realized this after opening the PR.
I feel like the specifications are not clear on this point, because it states that this exception should be raised in case of misalignment ... but because bit 0 is supposed to be zero it shouldn't happen.

[zarubaf]

Yes, I realized this after opening the PR. I feel like the specifications are not clear on this point, because it states that this exception should be raised in case of misalignment ... but because bit 0 is supposed to be zero it shouldn't happen.

Indeed, could be clearer about it. But I think it is exactly how you wrote it. It should trigger it, but you can't trigger it.