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Merge pull request #683 from pavel-demin/develop
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add output phase offset to vna
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@pavel-demin
pavel-demin authored Mar 4, 2018
2 parents 7c5a7da + a9cf2c0 commit 62384e8
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Showing 5 changed files with 289 additions and 85 deletions.
112 changes: 80 additions & 32 deletions projects/vna/block_design.tcl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -73,57 +73,71 @@ create_bd_port -dir O -from 7 -to 0 exp_p_tri_io

# Create axi_cfg_register
cell pavel-demin:user:axi_cfg_register:1.0 cfg_0 {
CFG_DATA_WIDTH 96
CFG_DATA_WIDTH 160
AXI_ADDR_WIDTH 32
AXI_DATA_WIDTH 32
}

# Create xlslice
cell xilinx.com:ip:xlslice:1.0 slice_0 {
DIN_WIDTH 96 DIN_FROM 0 DIN_TO 0 DOUT_WIDTH 1
DIN_WIDTH 160 DIN_FROM 0 DIN_TO 0 DOUT_WIDTH 1
} {
Din cfg_0/cfg_data
}

# Create xlslice
cell xilinx.com:ip:xlslice:1.0 slice_1 {
DIN_WIDTH 96 DIN_FROM 1 DIN_TO 1 DOUT_WIDTH 1
DIN_WIDTH 160 DIN_FROM 1 DIN_TO 1 DOUT_WIDTH 1
} {
Din cfg_0/cfg_data
}

# Create xlslice
cell xilinx.com:ip:xlslice:1.0 slice_2 {
DIN_WIDTH 96 DIN_FROM 2 DIN_TO 2 DOUT_WIDTH 1
DIN_WIDTH 160 DIN_FROM 2 DIN_TO 2 DOUT_WIDTH 1
} {
Din cfg_0/cfg_data
}

# Create xlslice
cell xilinx.com:ip:xlslice:1.0 slice_3 {
DIN_WIDTH 96 DIN_FROM 15 DIN_TO 8 DOUT_WIDTH 8
DIN_WIDTH 160 DIN_FROM 15 DIN_TO 8 DOUT_WIDTH 8
} {
Din cfg_0/cfg_data
Dout exp_p_tri_io
}

# Create xlslice
cell xilinx.com:ip:xlslice:1.0 slice_4 {
DIN_WIDTH 96 DIN_FROM 63 DIN_TO 32 DOUT_WIDTH 32
DIN_WIDTH 160 DIN_FROM 63 DIN_TO 32 DOUT_WIDTH 32
} {
Din cfg_0/cfg_data
}

# Create xlslice
cell xilinx.com:ip:xlslice:1.0 slice_5 {
DIN_WIDTH 96 DIN_FROM 79 DIN_TO 64 DOUT_WIDTH 16
DIN_WIDTH 160 DIN_FROM 95 DIN_TO 64 DOUT_WIDTH 32
} {
Din cfg_0/cfg_data
}

# Create xlslice
cell xilinx.com:ip:xlslice:1.0 slice_6 {
DIN_WIDTH 96 DIN_FROM 95 DIN_TO 80 DOUT_WIDTH 16
DIN_WIDTH 160 DIN_FROM 127 DIN_TO 96 DOUT_WIDTH 32
} {
Din cfg_0/cfg_data
}

# Create xlslice
cell xilinx.com:ip:xlslice:1.0 slice_7 {
DIN_WIDTH 160 DIN_FROM 143 DIN_TO 128 DOUT_WIDTH 16
} {
Din cfg_0/cfg_data
}

# Create xlslice
cell xilinx.com:ip:xlslice:1.0 slice_8 {
DIN_WIDTH 160 DIN_FROM 159 DIN_TO 144 DOUT_WIDTH 16
} {
Din cfg_0/cfg_data
}
Expand Down Expand Up @@ -174,32 +188,46 @@ cell xilinx.com:ip:dds_compiler:6.0 dds_0 {
DSP48_USE Minimal
NEGATIVE_SINE true
} {
S_AXIS_PHASE inter_0/M_AXIS
s_axis_phase_tdata inter_0/m_axis_tdata
s_axis_phase_tvalid inter_0/m_axis_tvalid
s_axis_phase_tready inter_0/m_axis_tready
m_axis_data_tready const_0/dout
aclk pll_0/clk_out1
aresetn slice_0/Dout
}

# RX

for {set i 0} {$i <= 3} {incr i} {
for {set i 0} {$i <= 1} {incr i} {

# Create xlslice
cell xilinx.com:ip:xlslice:1.0 adc_slice_$i {
DIN_WIDTH 32 DIN_FROM [expr 16 * ($i / 2) + 13] DIN_TO [expr 16 * ($i / 2)] DOUT_WIDTH 14
# Create xlconcat
cell xilinx.com:ip:xlconcat:2.1 concat_$i {
NUM_PORTS 2
IN0_WIDTH 32
IN1_WIDTH 32
} {
Din adc_0/m_axis_tdata
In0 inter_0/m_axis_tdata
In1 slice_[expr $i + 5]/Dout
}

}

for {set i 0} {$i <= 1} {incr i} {

# Create xlslice
cell xilinx.com:ip:xlslice:1.0 dds_slice_$i {
DIN_WIDTH 48 DIN_FROM [expr 24 * $i + 23] DIN_TO [expr 24 * $i] DOUT_WIDTH 24
# Create dds_compiler
cell xilinx.com:ip:dds_compiler:6.0 dds_[expr $i + 1] {
DDS_CLOCK_RATE 125
SPURIOUS_FREE_DYNAMIC_RANGE 138
FREQUENCY_RESOLUTION 0.2
PHASE_INCREMENT Streaming
PHASE_OFFSET Streaming
HAS_TREADY true
HAS_ARESETN true
HAS_PHASE_OUT false
PHASE_WIDTH 30
OUTPUT_WIDTH 24
DSP48_USE Minimal
OUTPUT_SELECTION Sine
} {
Din dds_0/m_axis_data_tdata
s_axis_phase_tdata concat_$i/dout
s_axis_phase_tvalid inter_0/m_axis_tvalid
m_axis_data_tready const_0/dout
aclk pll_0/clk_out1
aresetn slice_0/Dout
}

}
Expand All @@ -222,8 +250,8 @@ cell xilinx.com:ip:xbip_dsp48_macro:3.0 mult_4 {
B_WIDTH 16
P_WIDTH 15
} {
A dds_slice_1/Dout
B slice_5/Dout
A dds_1/m_axis_data_tdata
B slice_7/Dout
CARRYIN lfsr_0/m_axis_tdata
CLK pll_0/clk_out1
}
Expand All @@ -238,14 +266,14 @@ cell xilinx.com:ip:xbip_dsp48_macro:3.0 mult_5 {
B_WIDTH 16
P_WIDTH 15
} {
A dds_slice_1/Dout
B slice_6/Dout
A dds_2/m_axis_data_tdata
B slice_8/Dout
CARRYIN lfsr_0/m_axis_tdata
CLK pll_0/clk_out1
}

# Create xlconcat
cell xilinx.com:ip:xlconcat:2.1 concat_0 {
cell xilinx.com:ip:xlconcat:2.1 concat_2 {
NUM_PORTS 2
IN0_WIDTH 16
IN1_WIDTH 16
Expand All @@ -268,14 +296,34 @@ cell xilinx.com:ip:c_shift_ram:12.0 delay_0 {
cell pavel-demin:user:axis_zeroer:1.0 zeroer_0 {
AXIS_TDATA_WIDTH 32
} {
s_axis_tdata concat_0/dout
s_axis_tdata concat_2/dout
s_axis_tvalid delay_0/Q
M_AXIS dac_0/S_AXIS
aclk pll_0/clk_out1
}

# RX

for {set i 0} {$i <= 1} {incr i} {

# Create xlslice
cell xilinx.com:ip:xlslice:1.0 dds_slice_$i {
DIN_WIDTH 48 DIN_FROM [expr 24 * $i + 23] DIN_TO [expr 24 * $i] DOUT_WIDTH 24
} {
Din dds_0/m_axis_data_tdata
}

}

for {set i 0} {$i <= 3} {incr i} {

# Create xlslice
cell xilinx.com:ip:xlslice:1.0 adc_slice_$i {
DIN_WIDTH 32 DIN_FROM [expr 16 * ($i / 2) + 13] DIN_TO [expr 16 * ($i / 2)] DOUT_WIDTH 14
} {
Din adc_0/m_axis_tdata
}

# Create xbip_dsp48_macro
cell xilinx.com:ip:xbip_dsp48_macro:3.0 mult_$i {
INSTRUCTION1 RNDSIMPLE(A*B+CARRYIN)
Expand Down Expand Up @@ -411,7 +459,7 @@ cell pavel-demin:user:dna_reader:1.0 dna_0 {} {
}

# Create xlconcat
cell xilinx.com:ip:xlconcat:2.1 concat_1 {
cell xilinx.com:ip:xlconcat:2.1 concat_3 {
NUM_PORTS 3
IN0_WIDTH 32
IN1_WIDTH 64
Expand All @@ -428,7 +476,7 @@ cell pavel-demin:user:axi_sts_register:1.0 sts_0 {
AXI_ADDR_WIDTH 32
AXI_DATA_WIDTH 32
} {
sts_data concat_1/dout
sts_data concat_3/dout
}

# Create all required interconnections
Expand Down
50 changes: 39 additions & 11 deletions projects/vna/client/vna.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -490,6 +490,7 @@ def __init__(self):
for i in range(self.rateValue.count()):
self.rateValue.setItemData(i, Qt.AlignRight, Qt.TextAlignmentRole)
self.set_enabled(False)
self.stopSweep.setEnabled(False)
# read settings
settings = QSettings('vna.ini', QSettings.IniFormat)
self.read_cfg_settings(settings)
Expand Down Expand Up @@ -517,7 +518,10 @@ def __init__(self):
self.sizeValue.valueChanged.connect(self.set_size)
self.rateValue.currentIndexChanged.connect(self.set_rate)
self.corrValue.valueChanged.connect(self.set_corr)
self.levelValue.valueChanged.connect(self.set_level)
self.phase1Value.valueChanged.connect(self.set_phase1)
self.phase2Value.valueChanged.connect(self.set_phase2)
self.level1Value.valueChanged.connect(self.set_level1)
self.level2Value.valueChanged.connect(self.set_level2)
self.tabWidget.currentChanged.connect(self.update_tab)
# create timers
self.startTimer = QTimer(self)
Expand All @@ -526,7 +530,7 @@ def __init__(self):
self.sweepTimer.timeout.connect(self.sweep_timeout)

def set_enabled(self, enabled):
widgets = [self.corrValue, self.rateValue, self.levelValue, self.sizeValue, self.stopValue, self.startValue, self.openSweep, self.shortSweep, self.loadSweep, self.singleSweep, self.autoSweep]
widgets = [self.rateValue, self.level1Value, self.level2Value, self.corrValue, self.phase1Value, self.phase2Value, self.startValue, self.stopValue, self.sizeValue, self.openSweep, self.shortSweep, self.loadSweep, self.singleSweep, self.autoSweep]
for entry in widgets:
entry.setEnabled(enabled)

Expand All @@ -545,6 +549,7 @@ def stop(self):
self.connectButton.setText('Connect')
self.connectButton.setEnabled(True)
self.set_enabled(False)
self.stopSweep.setEnabled(False)

def timeout(self):
self.display_error('timeout')
Expand All @@ -554,11 +559,15 @@ def connected(self):
self.idle = False
self.set_rate(self.rateValue.currentIndex())
self.set_corr(self.corrValue.value())
self.set_level(self.levelValue.value())
self.set_phase1(self.phase1Value.value())
self.set_phase2(self.phase2Value.value())
self.set_level1(self.level1Value.value())
self.set_level2(self.level2Value.value())
self.set_gpio(1)
self.connectButton.setText('Disconnect')
self.connectButton.setEnabled(True)
self.set_enabled(True)
self.stopSweep.setEnabled(True)

def read_data(self):
while(self.socket.bytesAvailable() > 0):
Expand Down Expand Up @@ -613,14 +622,27 @@ def set_corr(self, value):
if self.idle: return
self.socket.write(struct.pack('<I', 4<<28 | int(value)))

def set_level(self, value):
def set_phase1(self, value):
if self.idle: return
self.socket.write(struct.pack('<I', 5<<28 | int(32766 * np.power(10.0, value / 20.0))))
self.socket.write(struct.pack('<I', 6<<28 | int(0)))
self.socket.write(struct.pack('<I', 5<<28 | int(value)))

def set_phase2(self, value):
if self.idle: return
self.socket.write(struct.pack('<I', 6<<28 | int(value)))

def set_level1(self, value):
if self.idle: return
data = 0 if value == -90 else int(32766 * np.power(10.0, value / 20.0))
self.socket.write(struct.pack('<I', 7<<28 | int(data)))

def set_level2(self, value):
if self.idle: return
data = 0 if value == -90 else int(32766 * np.power(10.0, value / 20.0))
self.socket.write(struct.pack('<I', 8<<28 | int(data)))

def set_gpio(self, value):
if self.idle: return
self.socket.write(struct.pack('<I', 7<<28 | int(value)))
self.socket.write(struct.pack('<I', 9<<28 | int(value)))

def sweep(self, mode):
if self.idle: return
Expand All @@ -631,7 +653,7 @@ def sweep(self, mode):
self.socket.write(struct.pack('<I', 0<<28 | int(self.sweep_start * 1000)))
self.socket.write(struct.pack('<I', 1<<28 | int(self.sweep_stop * 1000)))
self.socket.write(struct.pack('<I', 2<<28 | int(self.sweep_size)))
self.socket.write(struct.pack('<I', 8<<28))
self.socket.write(struct.pack('<I', 10<<28))
self.progressBar.setMinimum(0)
self.progressBar.setMaximum(self.sweep_size)
self.progressBar.setValue(0)
Expand All @@ -640,7 +662,7 @@ def cancel(self):
self.sweepTimer.stop()
self.auto = False
self.reading = False
self.socket.write(struct.pack('<I', 9<<28))
self.socket.write(struct.pack('<I', 11<<28))
self.progressBar.setValue(0)
self.set_enabled(True)

Expand Down Expand Up @@ -716,7 +738,10 @@ def write_cfg_settings(self, settings):
settings.setValue('addr', self.addrValue.text())
settings.setValue('rate', self.rateValue.currentIndex())
settings.setValue('corr', self.corrValue.value())
settings.setValue('level', self.levelValue.value())
settings.setValue('phase_1', self.phase1Value.value())
settings.setValue('phase_2', self.phase2Value.value())
settings.setValue('level_1', self.level1Value.value())
settings.setValue('level_2', self.level2Value.value())
settings.setValue('open_start', int(self.open.freq[0]))
settings.setValue('open_stop', int(self.open.freq[-1]))
settings.setValue('open_size', self.open.freq.size)
Expand Down Expand Up @@ -752,7 +777,10 @@ def read_cfg_settings(self, settings):
self.addrValue.setText(settings.value('addr', '192.168.1.100'))
self.rateValue.setCurrentIndex(settings.value('rate', 0, type = int))
self.corrValue.setValue(settings.value('corr', 0, type = int))
self.levelValue.setValue(settings.value('level', 0, type = int))
self.phase1Value.setValue(settings.value('phase_1', 0, type = int))
self.phase2Value.setValue(settings.value('phase_2', 0, type = int))
self.level1Value.setValue(settings.value('level_1', 0, type = int))
self.level2Value.setValue(settings.value('level_2', -90, type = int))
open_start = settings.value('open_start', 10, type = int)
open_stop = settings.value('open_stop', 60000, type = int)
open_size = settings.value('open_size', 6000, type = int)
Expand Down
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