replace xbip_dsp48_macro with dsp_macro

pavel-demin · Jun 26, 2021 · 646de8d · 646de8d
1 parent 90b8695
commit 646de8d
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Showing 35 changed files with 104 additions and 104 deletions.
diff --git a/projects/adc_test/block_design.tcl b/projects/adc_test/block_design.tcl
@@ -230,8 +230,8 @@ for {set i 0} {$i <= 1} {incr i} {
     aclk pll_0/clk_out1
   }
 
-  # Create xbip_dsp48_macro
-  cell xilinx.com:ip:xbip_dsp48_macro mult_$i {
+  # Create dsp_macro
+  cell xilinx.com:ip:dsp_macro mult_$i {
     INSTRUCTION1 RNDSIMPLE(A*B+CARRYIN)
     A_WIDTH.VALUE_SRC USER
     B_WIDTH.VALUE_SRC USER

diff --git a/projects/gate_test/block_design.tcl b/projects/gate_test/block_design.tcl
@@ -166,8 +166,8 @@ cell pavel-demin:user:axis_lfsr lfsr_0 {} {
   aresetn /rst_0/peripheral_aresetn
 }
 
-# Create xbip_dsp48_macro
-cell xilinx.com:ip:xbip_dsp48_macro mult_0 {
+# Create dsp_macro
+cell xilinx.com:ip:dsp_macro mult_0 {
   INSTRUCTION1 RNDSIMPLE(A*B+CARRYIN)
   A_WIDTH.VALUE_SRC USER
   B_WIDTH.VALUE_SRC USER

diff --git a/projects/iir_test/block_design.tcl b/projects/iir_test/block_design.tcl
@@ -135,8 +135,8 @@ cell pavel-demin:user:axis_zeroer zeroer_0 {
   aclk pll_0/clk_out1
 }
 
-# Create xbip_dsp48_macro
-cell xilinx.com:ip:xbip_dsp48_macro dsp_0 {
+# Create dsp_macro
+cell xilinx.com:ip:dsp_macro dsp_0 {
   INSTRUCTION1 A*B
   A_WIDTH.VALUE_SRC USER
   B_WIDTH.VALUE_SRC USER
@@ -149,8 +149,8 @@ cell xilinx.com:ip:xbip_dsp48_macro dsp_0 {
   CLK pll_0/clk_out1
 }
 
-# Create xbip_dsp48_macro
-cell xilinx.com:ip:xbip_dsp48_macro dsp_1 {
+# Create dsp_macro
+cell xilinx.com:ip:dsp_macro dsp_1 {
   INSTRUCTION1 A*B+C
   PIPELINE_OPTIONS Expert
   AREG_3 false
@@ -172,7 +172,7 @@ cell xilinx.com:ip:xbip_dsp48_macro dsp_1 {
   CLK pll_0/clk_out1
 }
 
-cell xilinx.com:ip:xbip_dsp48_macro dsp_2 {
+cell xilinx.com:ip:dsp_macro dsp_2 {
   INSTRUCTION1 A*B+C
   PIPELINE_OPTIONS Expert
   AREG_3 false

diff --git a/projects/impedance_controller/block_design.tcl b/projects/impedance_controller/block_design.tcl
@@ -191,8 +191,8 @@ cell pavel-demin:user:axis_lfsr lfsr_0 {} {
   aresetn slice_0/dout
 }
 
-# Create xbip_dsp48_macro
-cell xilinx.com:ip:xbip_dsp48_macro mult_4 {
+# Create dsp_macro
+cell xilinx.com:ip:dsp_macro mult_4 {
   INSTRUCTION1 RNDSIMPLE(A*B+CARRYIN)
   A_WIDTH.VALUE_SRC USER
   B_WIDTH.VALUE_SRC USER
@@ -249,8 +249,8 @@ for {set i 0} {$i <= 1} {incr i} {
 
 for {set i 0} {$i <= 3} {incr i} {
 
-  # Create xbip_dsp48_macro
-  cell xilinx.com:ip:xbip_dsp48_macro mult_$i {
+  # Create dsp_macro
+  cell xilinx.com:ip:dsp_macro mult_$i {
     INSTRUCTION1 RNDSIMPLE(A*B+CARRYIN)
     A_WIDTH.VALUE_SRC USER
     B_WIDTH.VALUE_SRC USER

diff --git a/projects/mcpha/gen.tcl b/projects/mcpha/gen.tcl
@@ -92,8 +92,8 @@ cell pavel-demin:user:axis_zeroer zeroer_0 {
   aclk /pll_0/clk_out1
 }
 
-# Create xbip_dsp48_macro
-cell xilinx.com:ip:xbip_dsp48_macro dsp_0 {
+# Create dsp_macro
+cell xilinx.com:ip:dsp_macro dsp_0 {
   INSTRUCTION1 A*B
   A_WIDTH.VALUE_SRC USER
   B_WIDTH.VALUE_SRC USER
@@ -106,8 +106,8 @@ cell xilinx.com:ip:xbip_dsp48_macro dsp_0 {
   CLK /pll_0/clk_out1
 }
 
-# Create xbip_dsp48_macro
-cell xilinx.com:ip:xbip_dsp48_macro dsp_1 {
+# Create dsp_macro
+cell xilinx.com:ip:dsp_macro dsp_1 {
   INSTRUCTION1 A*B+C
   PIPELINE_OPTIONS Expert
   AREG_3 false
@@ -129,7 +129,7 @@ cell xilinx.com:ip:xbip_dsp48_macro dsp_1 {
   CLK /pll_0/clk_out1
 }
 
-cell xilinx.com:ip:xbip_dsp48_macro dsp_2 {
+cell xilinx.com:ip:dsp_macro dsp_2 {
   INSTRUCTION1 A*B+C
   PIPELINE_OPTIONS Expert
   AREG_3 false

diff --git a/projects/pdm_test/block_design.tcl b/projects/pdm_test/block_design.tcl
@@ -197,8 +197,8 @@ cell pavel-demin:user:axis_lfsr lfsr_0 {} {
   aresetn slice_1/dout
 }
 
-# Create xbip_dsp48_macro
-cell xilinx.com:ip:xbip_dsp48_macro mult_0 {
+# Create dsp_macro
+cell xilinx.com:ip:dsp_macro mult_0 {
   INSTRUCTION1 RNDSIMPLE(A*B+CARRYIN)
   A_WIDTH.VALUE_SRC USER
   B_WIDTH.VALUE_SRC USER

diff --git a/projects/pulsed_nmr/rx.tcl b/projects/pulsed_nmr/rx.tcl
@@ -78,8 +78,8 @@ for {set i 0} {$i <= 3} {incr i} {
     din /adc_0/m_axis_tdata
   }
 
-  # Create xbip_dsp48_macro
-  cell xilinx.com:ip:xbip_dsp48_macro mult_$i {
+  # Create dsp_macro
+  cell xilinx.com:ip:dsp_macro mult_$i {
     INSTRUCTION1 RNDSIMPLE(A*B+CARRYIN)
     A_WIDTH.VALUE_SRC USER
     B_WIDTH.VALUE_SRC USER
@@ -245,8 +245,8 @@ cell pavel-demin:user:axi_axis_reader reader_0 {
   aresetn /rst_0/peripheral_aresetn
 }
 
-# Create xbip_dsp48_macro
-cell xilinx.com:ip:xbip_dsp48_macro mult_4 {
+# Create dsp_macro
+cell xilinx.com:ip:dsp_macro mult_4 {
   INSTRUCTION1 RNDSIMPLE(A*B+CARRYIN)
   A_WIDTH.VALUE_SRC USER
   B_WIDTH.VALUE_SRC USER

diff --git a/projects/pulsed_nmr/tx.tcl b/projects/pulsed_nmr/tx.tcl
@@ -119,8 +119,8 @@ cell pavel-demin:user:axis_lfsr lfsr_0 {} {
   aresetn /rst_0/peripheral_aresetn
 }
 
-# Create xbip_dsp48_macro
-cell xilinx.com:ip:xbip_dsp48_macro mult_0 {
+# Create dsp_macro
+cell xilinx.com:ip:dsp_macro mult_0 {
   INSTRUCTION1 RNDSIMPLE(A*B+CARRYIN)
   A_WIDTH.VALUE_SRC USER
   B_WIDTH.VALUE_SRC USER

diff --git a/projects/pulsed_nmr_122_88/rx.tcl b/projects/pulsed_nmr_122_88/rx.tcl
@@ -78,8 +78,8 @@ for {set i 0} {$i <= 3} {incr i} {
     din /adc_0/m_axis_tdata
   }
 
-  # Create xbip_dsp48_macro
-  cell xilinx.com:ip:xbip_dsp48_macro mult_$i {
+  # Create dsp_macro
+  cell xilinx.com:ip:dsp_macro mult_$i {
     INSTRUCTION1 RNDSIMPLE(A*B+CARRYIN)
     A_WIDTH.VALUE_SRC USER
     B_WIDTH.VALUE_SRC USER
@@ -245,8 +245,8 @@ cell pavel-demin:user:axi_axis_reader reader_0 {
   aresetn /rst_0/peripheral_aresetn
 }
 
-# Create xbip_dsp48_macro
-cell xilinx.com:ip:xbip_dsp48_macro mult_4 {
+# Create dsp_macro
+cell xilinx.com:ip:dsp_macro mult_4 {
   INSTRUCTION1 RNDSIMPLE(A*B+CARRYIN)
   A_WIDTH.VALUE_SRC USER
   B_WIDTH.VALUE_SRC USER

diff --git a/projects/pulsed_nmr_122_88/tx.tcl b/projects/pulsed_nmr_122_88/tx.tcl
@@ -119,8 +119,8 @@ cell pavel-demin:user:axis_lfsr lfsr_0 {} {
   aresetn /rst_0/peripheral_aresetn
 }
 
-# Create xbip_dsp48_macro
-cell xilinx.com:ip:xbip_dsp48_macro mult_0 {
+# Create dsp_macro
+cell xilinx.com:ip:dsp_macro mult_0 {
   INSTRUCTION1 RNDSIMPLE(A*B+CARRYIN)
   A_WIDTH.VALUE_SRC USER
   B_WIDTH.VALUE_SRC USER

diff --git a/projects/sdr_receiver_hpsdr/rx.tcl b/projects/sdr_receiver_hpsdr/rx.tcl
@@ -71,8 +71,8 @@ for {set i 0} {$i <= 15} {incr i} {
     din dds_[expr $i / 2]/m_axis_data_tdata
   }
 
-  # Create xbip_dsp48_macro
-  cell xilinx.com:ip:xbip_dsp48_macro mult_$i {
+  # Create dsp_macro
+  cell xilinx.com:ip:dsp_macro mult_$i {
     INSTRUCTION1 RNDSIMPLE(A*B+CARRYIN)
     A_WIDTH.VALUE_SRC USER
     B_WIDTH.VALUE_SRC USER

diff --git a/projects/sdr_receiver_hpsdr_122_88/rx.tcl b/projects/sdr_receiver_hpsdr_122_88/rx.tcl
@@ -72,8 +72,8 @@ for {set i 0} {$i <= 15} {incr i} {
     din dds_[expr $i / 2]/m_axis_data_tdata
   }
 
-  # Create xbip_dsp48_macro
-  cell xilinx.com:ip:xbip_dsp48_macro mult_$i {
+  # Create dsp_macro
+  cell xilinx.com:ip:dsp_macro mult_$i {
     INSTRUCTION1 RNDSIMPLE(A*B+CARRYIN)
     A_WIDTH.VALUE_SRC USER
     B_WIDTH.VALUE_SRC USER

diff --git a/projects/sdr_receiver_wide_122_88/block_design.tcl b/projects/sdr_receiver_wide_122_88/block_design.tcl
@@ -171,8 +171,8 @@ for {set i 0} {$i <= 3} {incr i} {
     din dds_[expr $i / 2]/m_axis_data_tdata
   }
 
-  # Create xbip_dsp48_macro
-  cell xilinx.com:ip:xbip_dsp48_macro mult_$i {
+  # Create dsp_macro
+  cell xilinx.com:ip:dsp_macro mult_$i {
     INSTRUCTION1 RNDSIMPLE(A*B+CARRYIN)
     A_WIDTH.VALUE_SRC USER
     B_WIDTH.VALUE_SRC USER
@@ -297,8 +297,8 @@ for {set i 0} {$i <= 1} {incr i} {
     din cfg_0/cfg_data
   }
 
-  # Create xbip_dsp48_macro
-  cell xilinx.com:ip:xbip_dsp48_macro mult_[expr $i + 4] {
+  # Create dsp_macro
+  cell xilinx.com:ip:dsp_macro mult_[expr $i + 4] {
     INSTRUCTION1 RNDSIMPLE(A*B+CARRYIN)
     A_WIDTH.VALUE_SRC USER
     B_WIDTH.VALUE_SRC USER

diff --git a/projects/sdr_transceiver_emb/rx.tcl b/projects/sdr_transceiver_emb/rx.tcl
@@ -61,8 +61,8 @@ for {set i 0} {$i <= 3} {incr i} {
     din dds_[expr $i / 2]/m_axis_data_tdata
   }
 
-  # Create xbip_dsp48_macro
-  cell xilinx.com:ip:xbip_dsp48_macro mult_$i {
+  # Create dsp_macro
+  cell xilinx.com:ip:dsp_macro mult_$i {
     INSTRUCTION1 RNDSIMPLE(A*B+CARRYIN)
     A_WIDTH.VALUE_SRC USER
     B_WIDTH.VALUE_SRC USER

diff --git a/projects/sdr_transceiver_emb/sp.tcl b/projects/sdr_transceiver_emb/sp.tcl
@@ -82,8 +82,8 @@ for {set i 0} {$i <= 1} {incr i} {
     din dds_0/m_axis_data_tdata
   }
 
-  # Create xbip_dsp48_macro
-  cell xilinx.com:ip:xbip_dsp48_macro mult_$i {
+  # Create dsp_macro
+  cell xilinx.com:ip:dsp_macro mult_$i {
     INSTRUCTION1 RNDSIMPLE(A*B+CARRYIN)
     A_WIDTH.VALUE_SRC USER
     B_WIDTH.VALUE_SRC USER

diff --git a/projects/sdr_transceiver_emb/tx.tcl b/projects/sdr_transceiver_emb/tx.tcl
@@ -323,8 +323,8 @@ cell pavel-demin:user:axis_lfsr lfsr_1 {} {
   aresetn /rst_0/peripheral_aresetn
 }
 
-# Create xbip_dsp48_macro
-cell xilinx.com:ip:xbip_dsp48_macro mult_1 {
+# Create dsp_macro
+cell xilinx.com:ip:dsp_macro mult_1 {
   INSTRUCTION1 RNDSIMPLE(A*B+CARRYIN)
   A_WIDTH.VALUE_SRC USER
   B_WIDTH.VALUE_SRC USER

diff --git a/projects/sdr_transceiver_emb_122_88/rx.tcl b/projects/sdr_transceiver_emb_122_88/rx.tcl
@@ -61,8 +61,8 @@ for {set i 0} {$i <= 3} {incr i} {
     din dds_[expr $i / 2]/m_axis_data_tdata
   }
 
-  # Create xbip_dsp48_macro
-  cell xilinx.com:ip:xbip_dsp48_macro mult_$i {
+  # Create dsp_macro
+  cell xilinx.com:ip:dsp_macro mult_$i {
     INSTRUCTION1 RNDSIMPLE(A*B+CARRYIN)
     A_WIDTH.VALUE_SRC USER
     B_WIDTH.VALUE_SRC USER

diff --git a/projects/sdr_transceiver_emb_122_88/sp.tcl b/projects/sdr_transceiver_emb_122_88/sp.tcl
@@ -82,8 +82,8 @@ for {set i 0} {$i <= 1} {incr i} {
     din dds_0/m_axis_data_tdata
   }
 
-  # Create xbip_dsp48_macro
-  cell xilinx.com:ip:xbip_dsp48_macro mult_$i {
+  # Create dsp_macro
+  cell xilinx.com:ip:dsp_macro mult_$i {
     INSTRUCTION1 RNDSIMPLE(A*B+CARRYIN)
     A_WIDTH.VALUE_SRC USER
     B_WIDTH.VALUE_SRC USER

diff --git a/projects/sdr_transceiver_emb_122_88/tx.tcl b/projects/sdr_transceiver_emb_122_88/tx.tcl
@@ -284,8 +284,8 @@ cell pavel-demin:user:axis_lfsr lfsr_1 {} {
   aresetn /rst_0/peripheral_aresetn
 }
 
-# Create xbip_dsp48_macro
-cell xilinx.com:ip:xbip_dsp48_macro mult_1 {
+# Create dsp_macro
+cell xilinx.com:ip:dsp_macro mult_1 {
   INSTRUCTION1 RNDSIMPLE(A*B+CARRYIN)
   A_WIDTH.VALUE_SRC USER
   B_WIDTH.VALUE_SRC USER

diff --git a/projects/sdr_transceiver_ft8/rx.tcl b/projects/sdr_transceiver_ft8/rx.tcl
@@ -67,7 +67,7 @@ for {set i 0} {$i <= 15} {incr i} {
     din dds_[expr $i / 2]/m_axis_data_tdata
   }
 
-  cell xilinx.com:ip:xbip_dsp48_macro mult_$i {
+  cell xilinx.com:ip:dsp_macro mult_$i {
     INSTRUCTION1 RNDSIMPLE(A*B+CARRYIN)
     A_WIDTH.VALUE_SRC USER
     B_WIDTH.VALUE_SRC USER

diff --git a/projects/sdr_transceiver_ft8/tx.tcl b/projects/sdr_transceiver_ft8/tx.tcl
@@ -78,8 +78,8 @@ cell pavel-demin:user:axis_lfsr lfsr_0 {} {
   aresetn slice_0/dout
 }
 
-# Create xbip_dsp48_macro
-cell xilinx.com:ip:xbip_dsp48_macro mult_0 {
+# Create dsp_macro
+cell xilinx.com:ip:dsp_macro mult_0 {
   INSTRUCTION1 RNDSIMPLE(A*B+CARRYIN)
   A_WIDTH.VALUE_SRC USER
   B_WIDTH.VALUE_SRC USER
@@ -94,8 +94,8 @@ cell xilinx.com:ip:xbip_dsp48_macro mult_0 {
   CLK /pll_0/clk_out1
 }
 
-# Create xbip_dsp48_macro
-cell xilinx.com:ip:xbip_dsp48_macro mult_1 {
+# Create dsp_macro
+cell xilinx.com:ip:dsp_macro mult_1 {
   INSTRUCTION1 RNDSIMPLE(A*B+CARRYIN)
   A_WIDTH.VALUE_SRC USER
   B_WIDTH.VALUE_SRC USER

diff --git a/projects/sdr_transceiver_ft8_122_88/rx.tcl b/projects/sdr_transceiver_ft8_122_88/rx.tcl
@@ -67,7 +67,7 @@ for {set i 0} {$i <= 31} {incr i} {
     din dds_[expr $i / 2]/m_axis_data_tdata
   }
 
-  cell xilinx.com:ip:xbip_dsp48_macro mult_$i {
+  cell xilinx.com:ip:dsp_macro mult_$i {
     INSTRUCTION1 RNDSIMPLE(A*B+CARRYIN)
     A_WIDTH.VALUE_SRC USER
     B_WIDTH.VALUE_SRC USER

diff --git a/projects/sdr_transceiver_ft8_122_88/tx.tcl b/projects/sdr_transceiver_ft8_122_88/tx.tcl
@@ -78,8 +78,8 @@ cell pavel-demin:user:axis_lfsr lfsr_0 {} {
   aresetn slice_0/dout
 }
 
-# Create xbip_dsp48_macro
-cell xilinx.com:ip:xbip_dsp48_macro mult_0 {
+# Create dsp_macro
+cell xilinx.com:ip:dsp_macro mult_0 {
   INSTRUCTION1 RNDSIMPLE(A*B+CARRYIN)
   A_WIDTH.VALUE_SRC USER
   B_WIDTH.VALUE_SRC USER
@@ -94,8 +94,8 @@ cell xilinx.com:ip:xbip_dsp48_macro mult_0 {
   CLK /pll_0/clk_out1
 }
 
-# Create xbip_dsp48_macro
-cell xilinx.com:ip:xbip_dsp48_macro mult_1 {
+# Create dsp_macro
+cell xilinx.com:ip:dsp_macro mult_1 {
   INSTRUCTION1 RNDSIMPLE(A*B+CARRYIN)
   A_WIDTH.VALUE_SRC USER
   B_WIDTH.VALUE_SRC USER

diff --git a/projects/sdr_transceiver_hpsdr/codec.tcl b/projects/sdr_transceiver_hpsdr/codec.tcl
@@ -136,8 +136,8 @@ cell pavel-demin:user:axis_lfsr lfsr_0 {} {
   aresetn /rst_0/peripheral_aresetn
 }
 
-# Create xbip_dsp48_macro
-cell xilinx.com:ip:xbip_dsp48_macro mult_0 {
+# Create dsp_macro
+cell xilinx.com:ip:dsp_macro mult_0 {
   INSTRUCTION1 RNDSIMPLE(A*B+CARRYIN)
   A_WIDTH.VALUE_SRC USER
   B_WIDTH.VALUE_SRC USER
@@ -158,8 +158,8 @@ cell pavel-demin:user:axis_lfsr lfsr_1 {} {
   aresetn /rst_0/peripheral_aresetn
 }
 
-# Create xbip_dsp48_macro
-cell xilinx.com:ip:xbip_dsp48_macro mult_1 {
+# Create dsp_macro
+cell xilinx.com:ip:dsp_macro mult_1 {
   INSTRUCTION1 RNDSIMPLE(A*B+CARRYIN)
   A_WIDTH.VALUE_SRC USER
   B_WIDTH.VALUE_SRC USER

diff --git a/projects/sdr_transceiver_hpsdr/rx.tcl b/projects/sdr_transceiver_hpsdr/rx.tcl
@@ -145,8 +145,8 @@ cell xilinx.com:ip:xlconstant const_0
 
 for {set i 0} {$i <= 9} {incr i} {
 
-  # Create xbip_dsp48_macro
-  cell xilinx.com:ip:xbip_dsp48_macro mult_$i {
+  # Create dsp_macro
+  cell xilinx.com:ip:dsp_macro mult_$i {
     INSTRUCTION1 RNDSIMPLE(A*B+CARRYIN)
     A_WIDTH.VALUE_SRC USER
     B_WIDTH.VALUE_SRC USER