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usb regs
Assumptions made on source code:
- looks like USB block is Faraday FUSB200.
- We have 15 Endpoints and 15 FIFO buffers.
- FIFO0 - FIFO13, 512 Byte each. FIFO14 - FIFO15 - 64 Byte each.
- location of usb descriptor target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/src/usb_table.c
Default
- EP 1 OUT; Bulk; = LP (Low priority downstream); RX0;
- EP 2 IN; Bulk; = US (upstream)
- EP 3 IN; Interrupt;
- EP 4 OUT; Interrupt;
- EP 5 OUT; Bulk; = HP (High priority downstream); RX1;
- EP 6 OUT; Bulk; = MP (Medium priority downstream); RX2;
- BIT7 - Forced to be Full-Speed Mod?
- BIT6 - 1 = HighSpeed is set (read only?)
- BIT5 - Chip Enable
- BIT4 - Chip Software Rese
- BIT3 - Enter Suspend Mode
- BIT2 - Enable global Int
- BIT1 - Half speed mode for FPGA test
- BIT0 - Enable remote wake-up;
- BIT7 - SET_CONFIGURATION has been executed
- BIT6
- BIT5
- BIT4
- BIT3
- BIT2
- BIT1
- BIT0
- BIT6 - Do not generate SOF
- BIT5 - Enter Test Mode
- BIT4 - Do not toggle sequence
- BIT3 - Do not append CRC
- BIT2 - Clear External Side Address
- BIT1 - EP0 loopback test
- BIT0 - 1 ?? set on usb 2.0 init. Clear FIFO
- BIT7
- BIT6
- BIT5
- BIT4 - TEST_PKY - Test packed.
- BIT3 - TEST_SE0_NAK. High-Speed quiescent state.
- BIT2 - TEST_K, High-Speed K state
- BIT1 - TEST_J, High-Speed J state
- BIT0 - Enable soft-detachment
According to FUSB200 doc:
DM(D-) DP(D+) Description
0 0 0: SE0
0 1 1: 'J' State
1 0 2: 'K' State
1 1 3: SE1
0: Control PHY to turn off 1.5K Ohm pull-up resistor
1: Control PHY to turn on 1.5K Ohm pull-up resistor
If TEST_PKY is set, the test packet must be filled into FIFO by DMA first.
- BIT7
- BIT6 -
- BIT5 - CX FIFO empty
- BIT4 - CX FIFO full
- BIT3 - CX FIFO clear
- BIT2 - set CX_STL, CX data stalled
- BIT1 - Test packet data transfer finished
- BIT0 - set CX_DONE, CX data transfer finished
- Write 32bit data to fifo
Theoretically INTR_MASK_BYTE should control INTR_SOURCE. Is it correct?
USB OUT FIFO
USB OUT FIFO
USB OUT FIFO
#define mUSB_REG_OUT_INT_ENABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_4_OFFSET, \
USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_4_OFFSET)&0x3f)
#define mUSB_REG_OUT_INT_DISABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_4_OFFSET, \
USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_4_OFFSET)&0xc0)
USB IN FIFO
USB IN FIFO
#define mUSB_STATUS_IN_INT_ENABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_6_OFFSET, \
USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)&0xbf)
#define mUSB_STATUS_IN_INT_DISABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_6_OFFSET, \
USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)|0xc0)
- BIT7 - group INTR 7
- BIT6 - group INTR 6
- BIT5 - group INTR 5
- BIT4 - group INTR 4
- BIT3 - group INTR 3
- BIT2 - group INTR 2
- BIT1 - group INTR 1
- BIT0 - group INTR 0
These bits indicate if fallowing groups got some interrupt.
- BIT7 - abort interrupt? should be cleared first?
- BIT6 -
- BIT5 - (abort int on fotg210, may be here too?)
- BIT4 - ep0 CMD_FAIL (error)
- BIT3 - ep0 CMD_END
- BIT2 - EP0-OUT packet
- BIT1 - EP0-IN packet
- BIT0 - EP0-SETUP packet
....
- BIT1 - FIFO0 OUT - short packet
- BIT0 - FIFO0 OUT - data
- BIT7 - FIFO15 OUT - short packet.
- BIT6 - FIFO15 OUT - vUsb_Reg_Out(). Pending data in fifo for EP4. We need to read it out.
- BIT4 - FIFO14 OUT
- BIT2 - FIFO13 OUT
- BIT0 - FIFO12 OUT
- BIT1 - FIFO1 IN
- BIT0 - FIFO0 IN
- BIT6 - FIFO14 IN - vUsb_Status_In()
- BIT11 - device wake up
- BIT10 - device idle
- BIT9 - DMA error
- BIT8 - DMA finnished
- BIT7 - RX0BTYE_INT - Zero-Length-Packet Rx
- BIT6 - TX0BTYE_INT - Zero-Length-Packet Tx
- BIT5 - ISO seq abort
- BIT4 - ISO seq error
- BIT3 - USB resume
- BIT2 - USB suspend
- BIT1 - USB reset interrupt.
comment: not matching layout with fotg210.. some thing wrong?
code use: ZM_FUSB_BASE+0x30+(EPn-1)
(0x0F | FIFOn << 4) = OUT
(0xF0 | FIFOn) = IN
probably incorrect interpretation. It should be FUSB_REG_IDLE_CNT
set suspend delay in ms
for FIFOn see mUsbFIFOMap registers.
Current configuration:
- 0x2f 0x00
- 0x30 0x0f <- EP1 = OUT + Start FIFO0
- 0x31 0xf2 <- EP2 = IN + Start FIFO2
- 0x32 0xfe <- EP3 = IN + Start FIFO14
- 0x33 0xff <- EP4 = OUT + Start FIFO15
- 0x34 0x4f
- 0x35 0x6f
- 0x36 0x00
- 0x37 0x00
- 0x38 0x00
- 0x39 0x00
- 0x3a 0x00
- 0x3b 0x00
- 0x3c 0x00
- 0x3d 0x00
- BIT0 - BIT7; low size regs. Max size 0x7ff (ZM_EP_IN_MAX_SIZE_LOW_OFFSET + ZM_EP_IN_MAX_SIZE_HIGH_OFFSET)
Current configuration:
- 0x3e 0x00
- 0x40 0x00
- 0x42 0x00
- 0x44 0x40
- 0x46 0x00
- 0x48 0x00
- 0x4a 0x00
- 0x4c 0x00
- 0x4e 0x00
- 0x50 0x00
- 0x52 0x00
- 0x54 0x00
- 0x56 0x00
- 0x58 0x00
- 0x5a 0x00
- 0x5c 0x00
-
BIT7
-
BIT6
-
BIT5
-
BIT4 - mUsbEPinRsTgSet
-
BIT3 - mUsbEPinStallSet
-
BIT0 - BIT2; High size regs These offset + 2 Byte step for each endpoint.
For example EP0 = +0x00; EP1 = +0x02; or offset+(EPn << 1). In these address space will fit 15 endpoints. -
0x3f 0x00
-
0x41 0x02
-
0x43 0x22
-
0x45 0x20
-
0x47 0x02
-
0x49 0x02
-
0x4b 0x02
-
0x4d 0x00
-
0x4f 0x00
-
0x51 0x00
-
0x53 0x00
-
0x55 0x00
-
0x57 0x00
-
0x59 0x00
-
0x5b 0x00
-
0x5d 0x00
- BIT0 - BIT7; low size regs. Max size 0x7ff (ZM_EP_OUT_MAX_SIZE_LOW_OFFSET + ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET)
- BIT7
- BIT6
- BIT5
- BIT4 - mUsbEPoutRsTgSet
- BIT3 - mUsbEPoutStallSet
- BIT0 - BIT2; High size regs
These offset + 2 Byte step for each endpoint.
For example EP0 = +0x00; EP1 = +0x02; or offset+(EPn << 1). In these address space will fit 15 endpoints.
- BIT7
- BIT6
- BIT5
- BIT4 - Direction: 0 - OUT; 1 - IN.
- BIT0 - BIT3: assigned EP number.
Current layout:
- 0x80 0x01 - EP1 OUT
- 0x81 0x01 - EP1 OUT
- 0x82 0x12 - EP2 IN
- 0x83 0x12 - EP2 IN
- 0x84 0x05
- 0x85 0x05
- 0x86 0x06
- 0x87 0x06
- 0x88 0x00
- 0x89 0x00
- 0x8a 0x00
- 0x8b 0x00
- 0x8c 0x00
- 0x8d 0x00
- 0x8e 0x13
- 0x8f 0x04
-
BIT7 - If EPn use more then one FIFO, then this bit should be on the first
-
BIT6
-
BIT5
-
BIT4 - Block size: 0 - 64/512; 1 - 128/1024. It depends on initial FIFO size.
-
BIT2 - BIT3; number of FIFO blocks or better to say extra blocks? 0 - no more blocks; 1 - one block; 2 - two blocks.
-
BIT0 - BIT1; EP type: 0x1 - Iso; 0x2 - Bulk, 0x3 - Intr;
-
0x90 0x86 <- FIFO0: Bulk | + one block (0x91) | size 512
-
0x91 0x06
-
0x92 0x86
-
0x93 0x06
-
0x94 0x86
-
0x95 0x06
-
0x96 0x86
-
0x97 0x06
-
0x98 0x00
-
0x99 0x00
-
0x9a 0x00
-
0x9b 0x00
-
0x9c 0x00
-
0x9d 0x00
-
0x9e 0x83
-
0x9f 0x83
- BIT0 - BIT2 - high offset of byte count in fifo.
or known as ZM_EP3_BYTE_COUNT_HIGH_OFFSET
BIT3 - 1 xfer done?
comments: after sending data from target to host, set BIT3
or known ZM_EP4_BYTE_COUNT_HIGH_OFFSET
BIT4 - 1 - reset fifo; 0 - disable reset?
comments: probably compatible with ZM_EP3_BYTE_COUNT_HIGH_OFFSET.
These name reg do not fit to pattern!!! Compare with 0x3e, 0x3f and 0x5e, 0x5f.
If we have 0x3e, 0x3f and 0x5e, 0x5f, why do we need this register?
or known as ZM_EP3_BYTE_COUNT_LOW_OFFSET
size of data in fifo buffer? never used?
or known as ZM_EP4_BYTE_COUNT_LOW_OFFSET
size of data in fifo buffer. Maximum size of EP4 should be 64 Bytes. If reported value is bigger, then buffer is defiantly corrupt.
or known as FUSB_REG_FIFO0_DP
32bit data. Probably FIFO14 offset.. not EP
32bit data. Probably FIFO15 offset.. not EP
0x1 - 1 Byte, 0x3 - 2 Byte, 0x7 - 3 Byte; 0xf - 4 Byte.
we miss 7 bytes here
BIT10 - 1 - enable MP (EP6) downstream stream mode
BIT9 - 1 - enable MP (EP6) downstream DMA mode
BIT8 - 1 - enable HP (EP5) downstream DMA mode
BIT7 - 1 - enable HP (EP5) downstream stream mode
BIT6 - 1 - enable LP downstream stream mode
BIT5 - define the host dma buffer size - 4096(00) 8192 (01) 16384(10) 32768(11) bytes
BIT4 - ^
BIT3 - 0 - enable upstream stream mode: 1 - enable upstream packed mode;
BIT2 - 0 - Set into 64 byte mode (full speed) 1 - Set into 512 byte mode (usb highspeed)
BIT1 - 0 - disable upstream dma mode; 1 - enable upstream dma mode
BIT0 - 0 - disable LP down stream dma mode; 1 - eanble LP down stream dma mode
comments: ryan: 04/01: bit0 could disable lpdn dma, which is good at debugging while async_fifo have problem, we could disable this and check the fifo_rcv_size to see if we have correct at fifo or not LP - lo priotiry; MP - middle priority; HP - High priority;
set stream mode packet buffer critirea
0x0 = disable stream mode or 1 packet. So 0x9 is 10 packets?
set stream mode timeout critirea. the unit is 32 USB (30Mhz) clock cycles.
BIT0 - reset usb dma.