A FPGA friendly 32 bit RISC-V CPU implementation

CNN accelerator implemented with Spinal HDL

客制化机械键盘——从0开始全套资料

A reimplementation of a tiny stack CPU

[HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning

Clio, ASPLOS'22.

High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)

An High-Performance SLAM Hardware Accelerator Implementation for FPGA

SpinalHDL - Cryptography libraries

Translated SpinalHDL-Doc(v1.7.2) into Chinese

The SpinalHDL design of the Proteus core, an extensible RISC-V core.

A re-creation of a Cosmac ELF computer, Coded in SpinalHDL

Wrappers for open source FPU hardware implementations.

shdl6800: A 6800 processor written in SpinalHDL

The sources of the online SpinalHDL doc

Docker Development Environment for SpinalHDL

CNN accelerator implemented with Spinal HDL

Forth for the J1-CPU

Matrix Multiplication in Hardware

Custom Coprocessor Interface for VexRiscv