[Scratchpads] Needed packages for scratchpads and ahb peripheral bus #2458
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| localparam DSCR_ARBIT_NUM_IN = 3; | ||
| localparam ISCR_ARBIT_NUM_IN = 4; | ||
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| typedef enum logic [$clog2(ISCR_ARBIT_NUM_IN)-1:0] { |
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| typedef enum logic [$clog2(ISCR_ARBIT_NUM_IN)-1:0] { | |
| typedef enum logic [$clog2( | |
| ISCR_ARBIT_NUM_IN | |
| )-1:0] { |
| ISCR_ARBIT_FRONTEND | ||
| } iscr_arbit_e; | ||
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| typedef enum logic [$clog2(DSCR_ARBIT_NUM_IN)-1:0] { |
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| typedef enum logic [$clog2(DSCR_ARBIT_NUM_IN)-1:0] { | |
| typedef enum logic [$clog2( | |
| DSCR_ARBIT_NUM_IN | |
| )-1:0] { |
|
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| module address_decoder import address_decoder_pkg::*;#( | ||
| parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, | ||
| parameter type exception_t = logic, | ||
| parameter ADDR_WIDTH = 32 |
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| module address_decoder import address_decoder_pkg::*;#( | |
| parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, | |
| parameter type exception_t = logic, | |
| parameter ADDR_WIDTH = 32 | |
| module address_decoder | |
| import address_decoder_pkg::*; | |
| #( | |
| parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, | |
| parameter type exception_t = logic, | |
| parameter ADDR_WIDTH = 32 |
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| input logic clk_i, | ||
| input logic rst_ni, |
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| input logic clk_i, | |
| input logic rst_ni, | |
| input logic clk_i, | |
| input logic rst_ni, |
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| input logic addr_valid_i, // Input address is valid | ||
| input logic [ADDR_WIDTH-1:0] addr_i, // Address to be decoded |
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| input logic addr_valid_i, // Input address is valid | |
| input logic [ADDR_WIDTH-1:0] addr_i, // Address to be decoded | |
| input logic addr_valid_i, // Input address is valid | |
| input logic [ADDR_WIDTH-1:0] addr_i, // Address to be decoded |
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| input logic dscr_en_i, // From CSR | ||
| input logic iscr_en_i, // From CSR | ||
| input logic ahb_periph_en_i, // From CSR | ||
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| input logic [CVA6Cfg.XLEN-1:0] exception_code_i, | ||
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| output exception_t ex_o, | ||
| output addr_dec_mode_e select_mem_o |
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| input logic dscr_en_i, // From CSR | |
| input logic iscr_en_i, // From CSR | |
| input logic ahb_periph_en_i, // From CSR | |
| input logic [CVA6Cfg.XLEN-1:0] exception_code_i, | |
| output exception_t ex_o, | |
| output addr_dec_mode_e select_mem_o | |
| input logic dscr_en_i, // From CSR | |
| input logic iscr_en_i, // From CSR | |
| input logic ahb_periph_en_i, // From CSR | |
| input logic [CVA6Cfg.XLEN-1:0] exception_code_i, | |
| output exception_t ex_o, | |
| output addr_dec_mode_e select_mem_o |
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| assign match_dscr_region = config_pkg::is_inside_data_scratchpad(CVA6Cfg, {{64-ADDR_WIDTH{1'b0}}, addr_i}); | ||
| assign match_iscr_region = config_pkg::is_inside_instruction_scratchpad(CVA6Cfg, {{64-ADDR_WIDTH{1'b0}}, addr_i}); | ||
| assign match_any_ahbperiph_region = config_pkg::is_inside_ahbperiph_regions(CVA6Cfg, {{64-ADDR_WIDTH{1'b0}}, addr_i}); |
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| assign match_dscr_region = config_pkg::is_inside_data_scratchpad(CVA6Cfg, {{64-ADDR_WIDTH{1'b0}}, addr_i}); | |
| assign match_iscr_region = config_pkg::is_inside_instruction_scratchpad(CVA6Cfg, {{64-ADDR_WIDTH{1'b0}}, addr_i}); | |
| assign match_any_ahbperiph_region = config_pkg::is_inside_ahbperiph_regions(CVA6Cfg, {{64-ADDR_WIDTH{1'b0}}, addr_i}); | |
| assign match_dscr_region = config_pkg::is_inside_data_scratchpad( | |
| CVA6Cfg, {{64 - ADDR_WIDTH{1'b0}}, addr_i} | |
| ); | |
| assign match_iscr_region = config_pkg::is_inside_instruction_scratchpad( | |
| CVA6Cfg, {{64 - ADDR_WIDTH{1'b0}}, addr_i} | |
| ); | |
| assign match_any_ahbperiph_region = config_pkg::is_inside_ahbperiph_regions( | |
| CVA6Cfg, {{64 - ADDR_WIDTH{1'b0}}, addr_i} | |
| ); |
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| endmodule |
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| endmodule | |
| endmodule |
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| input ahb_req_t ahb_s_req_i, | ||
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| // Request from AHB acknowledged | ||
| input logic req_ack_i, |
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| input logic req_ack_i, | |
| input logic req_ack_i, |
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| end | ||
| // Go to SEQ if this becomes a BURST |
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| end | |
| // Go to SEQ if this becomes a BURST | |
| end // Go to SEQ if this becomes a BURST |
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| end | ||
| else if (ahb_s_req_i.htrans == AHB_TRANS_BUSY) state_d = S_BUSY; |
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| end | |
| else if (ahb_s_req_i.htrans == AHB_TRANS_BUSY) state_d = S_BUSY; | |
| end else if (ahb_s_req_i.htrans == AHB_TRANS_BUSY) state_d = S_BUSY; |
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| end | ||
| else if (ahb_s_req_i.hburst == AHB_BURST_INCR) begin |
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| end | |
| else if (ahb_s_req_i.hburst == AHB_BURST_INCR) begin | |
| end else if (ahb_s_req_i.hburst == AHB_BURST_INCR) begin |
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| if (ahb_s_req_i.hwrite) state_d = S_NONSEQ_WRITE; | ||
| else state_d = S_NONSEQ_READ; | ||
| end |
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| if (ahb_s_req_i.hwrite) state_d = S_NONSEQ_WRITE; | |
| else state_d = S_NONSEQ_READ; | |
| end | |
| if (ahb_s_req_i.hwrite) state_d = S_NONSEQ_WRITE; | |
| else state_d = S_NONSEQ_READ; | |
| end |
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| always_comb begin : p_ahb_outputs | ||
| hready_d = 1'b1; | ||
| hresp_d = 1'b0; // Exception not yet supported, no errors are sent to AHB BUS |
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| hresp_d = 1'b0; // Exception not yet supported, no errors are sent to AHB BUS | |
| hresp_d = 1'b0; // Exception not yet supported, no errors are sent to AHB BUS |
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| vaddr_d = vaddr_q; | ||
| wdata_d = wdata_q; | ||
| data_req_d = 1'b0; | ||
| data_we_d = 1'b0; | ||
| data_be_d = '0; // TODO: Determine if should be set depending of size or not? | ||
| size_d = size_q; |
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| vaddr_d = vaddr_q; | |
| wdata_d = wdata_q; | |
| data_req_d = 1'b0; | |
| data_we_d = 1'b0; | |
| data_be_d = '0; // TODO: Determine if should be set depending of size or not? | |
| size_d = size_q; | |
| vaddr_d = vaddr_q; | |
| wdata_d = wdata_q; | |
| data_req_d = 1'b0; | |
| data_we_d = 1'b0; | |
| data_be_d = '0; // TODO: Determine if should be set depending of size or not? | |
| size_d = size_q; |
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| assign req_port_o.data_id = '0; // Not supported: next req is sent when previous one is done | ||
| assign req_port_o.kill_req = '0; // Not supported: AHB master cannot kill a req |
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| assign req_port_o.data_id = '0; // Not supported: next req is sent when previous one is done | |
| assign req_port_o.kill_req = '0; // Not supported: AHB master cannot kill a req | |
| assign req_port_o.data_id = '0; // Not supported: next req is sent when previous one is done | |
| assign req_port_o.kill_req = '0; // Not supported: AHB master cannot kill a req |
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| logic [DSCR_ARBIT_NUM_IN-1:0] arb_req; | ||
| logic arb_gnt; | ||
| dscr_arbit_e arb_idx; | ||
| logic arb_idx_valid; |
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| logic [DSCR_ARBIT_NUM_IN-1:0] arb_req; | |
| logic arb_gnt; | |
| dscr_arbit_e arb_idx; | |
| logic arb_idx_valid; | |
| logic [DSCR_ARBIT_NUM_IN-1:0] arb_req; | |
| logic arb_gnt; | |
| dscr_arbit_e arb_idx; | |
| logic arb_idx_valid; |
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| sram_ctrl_addr = ld_req_port_i.vaddr; | ||
| sram_ctrl_we = ld_req_port_i.data_we; | ||
| sram_ctrl_be = ld_req_port_i.data_be; | ||
| sram_ctrl_wdata = ld_req_port_i.data_wdata; | ||
| sram_req_id = ld_req_port_i.data_id; |
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| sram_ctrl_addr = ld_req_port_i.vaddr; | |
| sram_ctrl_we = ld_req_port_i.data_we; | |
| sram_ctrl_be = ld_req_port_i.data_be; | |
| sram_ctrl_wdata = ld_req_port_i.data_wdata; | |
| sram_req_id = ld_req_port_i.data_id; | |
| sram_ctrl_addr = ld_req_port_i.vaddr; | |
| sram_ctrl_we = ld_req_port_i.data_we; | |
| sram_ctrl_be = ld_req_port_i.data_be; | |
| sram_ctrl_wdata = ld_req_port_i.data_wdata; | |
| sram_req_id = ld_req_port_i.data_id; |
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| ld_req_port_o.data_rdata = sram_resp_rdata; | ||
| ld_req_port_o.data_gnt = sram_resp_gnt; |
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| ld_req_port_o.data_rdata = sram_resp_rdata; | |
| ld_req_port_o.data_gnt = sram_resp_gnt; | |
| ld_req_port_o.data_rdata = sram_resp_rdata; | |
| ld_req_port_o.data_gnt = sram_resp_gnt; |
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| ld_req_port_o.data_rid = sram_resp_rid; | ||
| ld_req_port_o.data_ruser = '0; |
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| ld_req_port_o.data_rid = sram_resp_rid; | |
| ld_req_port_o.data_ruser = '0; | |
| ld_req_port_o.data_rid = sram_resp_rid; | |
| ld_req_port_o.data_ruser = '0; |
| ld_req_port_o.data_rid = sram_resp_rid; | ||
| ld_req_port_o.data_ruser = '0; | ||
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| ahb_req_port_i = '0; |
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| ahb_req_port_i = '0; | |
| ahb_req_port_i = '0; |
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| ahb_req_port_i = '0; | ||
| end else if (arb_idx == DSCR_ARBIT_STORE && arb_idx_valid) begin | ||
| sram_ctrl_req = st_req_port_i.data_req && !st_req_sent && !st_req_port_i.kill_req; |
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| sram_ctrl_req = st_req_port_i.data_req && !st_req_sent && !st_req_port_i.kill_req; | |
| sram_ctrl_req = st_req_port_i.data_req && !st_req_sent && !st_req_port_i.kill_req; |
| ld_req_port_o = '0; | ||
| ahb_req_port_i = '0; | ||
| end else if (arb_idx == DSCR_ARBIT_AHB && arb_idx_valid) begin | ||
| sram_ctrl_req = ahb_req_port_o.data_req; |
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| sram_ctrl_req = ahb_req_port_o.data_req; | |
| sram_ctrl_req = ahb_req_port_o.data_req; |
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| logic [ ISCR_ARBIT_NUM_IN-1:0] arb_req; | ||
| logic arb_gnt; | ||
| iscr_arbit_e arb_idx; | ||
| logic arb_idx_valid; |
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| logic [ ISCR_ARBIT_NUM_IN-1:0] arb_req; | |
| logic arb_gnt; | |
| iscr_arbit_e arb_idx; | |
| logic arb_idx_valid; | |
| logic [ISCR_ARBIT_NUM_IN-1:0] arb_req; | |
| logic arb_gnt; | |
| iscr_arbit_e arb_idx; | |
| logic arb_idx_valid; |
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| ld_req_port_o = '0; | ||
| ahb_req_port_i = '0; |
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| ld_req_port_o = '0; | |
| ahb_req_port_i = '0; | |
| ld_req_port_o = '0; | |
| ahb_req_port_i = '0; |
…dedicated bus for eavery target (dcache, dscr, iscr, periphe bus)
| end else if (st_select_mem == address_decoder_pkg::DECODER_MODE_AHB_PERIPH) begin | ||
| commit_ready_o = ahbperiph_ready_i; | ||
| rvfi_mem_paddr_o = speculative_queue_n[speculative_read_pointer_q].address; | ||
| end else if (st_select_mem == address_decoder_pkg::DECODER_MODE_CACHE) begin // DCACHE |
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| end else if (st_select_mem == address_decoder_pkg::DECODER_MODE_CACHE) begin // DCACHE | |
| end else if (st_select_mem == address_decoder_pkg::DECODER_MODE_CACHE) begin // DCACHE |
|
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| @@ -133,7 +134,27 @@ module load_store_unit | |||
| output logic itlb_miss_o, | |||
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| output logic itlb_miss_o, | |
| output logic itlb_miss_o, |
| @@ -133,7 +134,27 @@ | |||
| output logic itlb_miss_o, | |||
| // Data TLB miss - PERF_COUNTERS | |||
| output logic dtlb_miss_o, | |||
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| output logic dtlb_miss_o, | |
| output logic dtlb_miss_o, |
| input logic ahbperiph_ld_ex_i, | ||
| output scratchpad_req_i_t ahbperiph_st_req_port_o, | ||
| input logic ahbperiph_st_ready_i, | ||
| input logic ahbperiph_st_ex_i, | ||
| // Data cache request output - CACHES | ||
| input dcache_req_o_t [2:0] dcache_req_ports_i, |
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| input dcache_req_o_t [2:0] dcache_req_ports_i, | |
| input dcache_req_o_t [ 2:0] dcache_req_ports_i, |
|
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…e ahb slave and ahb master at IOs
… periph bus controller
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| parameter type rvfi_probes_instr_t = | ||
| `RVFI_PROBES_INSTR_T(CVA6Cfg), | ||
| parameter type rvfi_probes_csr_t = | ||
| `RVFI_PROBES_CSR_T(CVA6Cfg), |
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| parameter type rvfi_probes_instr_t = | |
| `RVFI_PROBES_INSTR_T(CVA6Cfg), | |
| parameter type rvfi_probes_csr_t = | |
| `RVFI_PROBES_CSR_T(CVA6Cfg), | |
| parameter type rvfi_probes_instr_t = `RVFI_PROBES_INSTR_T(CVA6Cfg), | |
| parameter type rvfi_probes_csr_t = `RVFI_PROBES_CSR_T(CVA6Cfg), |
| @@ -291,12 +321,18 @@ module cva6 | |||
| input logic time_irq_i, | |||
| // Debug (async) request - SUBSYSTEM | |||
| input logic debug_req_i, | |||
| // Probes to build RVFI, can be left open when not used - RVFI | |||
| // Probes to build RVFI, can be left open when not used - RVFI | |||
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| // Probes to build RVFI, can be left open when not used - RVFI | |
| // Probes to build RVFI, can be left open when not used - RVFI |
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| iscr_ahb_s_req_i = '0; | ||
| dscr_ahb_s_req_i = '0; |
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| iscr_ahb_s_req_i = '0; | |
| dscr_ahb_s_req_i = '0; | |
| iscr_ahb_s_req_i = '0; | |
| dscr_ahb_s_req_i = '0; |
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| .clk_i (clk_i), | ||
| .rst_ni (rst_ni), | ||
| .ahb_p_resp_i (ahb_p_resp_i), | ||
| .ahb_p_req_o (ahb_p_req_o), | ||
| .ld_req_port_i (ahbperiph_req_port_ld_periph), | ||
| .ld_req_port_o (ahbperiph_req_port_periph_ld), | ||
| .ld_ex_o (ahbperiph_ex_periph_ld), | ||
| .st_req_port_i (ahbperiph_req_port_st_periph), | ||
| .st_ready_o (ahbperiph_ready_periph_st), | ||
| .st_ex_o (ahbperiph_ex_periph_st) |
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| .clk_i (clk_i), | |
| .rst_ni (rst_ni), | |
| .ahb_p_resp_i (ahb_p_resp_i), | |
| .ahb_p_req_o (ahb_p_req_o), | |
| .ld_req_port_i (ahbperiph_req_port_ld_periph), | |
| .ld_req_port_o (ahbperiph_req_port_periph_ld), | |
| .ld_ex_o (ahbperiph_ex_periph_ld), | |
| .st_req_port_i (ahbperiph_req_port_st_periph), | |
| .st_ready_o (ahbperiph_ready_periph_st), | |
| .st_ex_o (ahbperiph_ex_periph_st) | |
| .clk_i (clk_i), | |
| .rst_ni (rst_ni), | |
| .ahb_p_resp_i (ahb_p_resp_i), | |
| .ahb_p_req_o (ahb_p_req_o), | |
| .ld_req_port_i(ahbperiph_req_port_ld_periph), | |
| .ld_req_port_o(ahbperiph_req_port_periph_ld), | |
| .ld_ex_o (ahbperiph_ex_periph_ld), | |
| .st_req_port_i(ahbperiph_req_port_st_periph), | |
| .st_ready_o (ahbperiph_ready_periph_st), | |
| .st_ex_o (ahbperiph_ex_periph_st) |
|
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This PR aims at integrate features developed by Bosch :