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[Scratchpads] Needed packages for scratchpads and ahb peripheral bus #2458

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1b8f2ad
Add packages for scratchpad and AHB periph.
CoralieAllioux Aug 23, 2024
e6b4236
Merge branch 'scratchpad-periphbus-packages' into feature/scratchpads
CoralieAllioux Aug 23, 2024
887be36
Remove patch
CoralieAllioux Aug 23, 2024
b3feeb7
Add address decoder for scratchpad and ahb periph regions
CoralieAllioux Aug 23, 2024
b58ae5d
Merge branch 'scratchpads/address_decoder' into feature/scratchpads
CoralieAllioux Aug 23, 2024
2ab02dd
Add parameters for ahb peripheral bus, data and instruction scratchpads
CoralieAllioux Aug 26, 2024
aa276ed
Add new parameters in all cva6 configurations
CoralieAllioux Aug 26, 2024
ba33f04
Add function to check if an address is inside scratchpads / ahb peirp…
CoralieAllioux Aug 26, 2024
b0aa116
Apply verible
CoralieAllioux Aug 26, 2024
2aae707
Merge branch 'scratchpads/parameters' into feature/scratchpads
CoralieAllioux Aug 27, 2024
400f176
Add ahb master adapter: used for ahb peripheral bus
CoralieAllioux Aug 26, 2024
a105964
Merge branch 'periph_bus/ahb_master' into feature/scratchpads
CoralieAllioux Aug 27, 2024
273a67a
Add AHB peripheral bus module
CoralieAllioux Aug 26, 2024
679d19b
Merge branch 'periph_bus/periph_bus' into feature/scratchpads
CoralieAllioux Aug 27, 2024
b10e82d
Add sram_controller: used for scratchpads
CoralieAllioux Aug 26, 2024
2f76258
Merge branch 'scratchpad/sram_controller' into feature/scratchpads
CoralieAllioux Aug 27, 2024
0b39bcf
Add AHB slave module
CoralieAllioux Aug 29, 2024
dd817f5
Add ahb slave in flist and missing files
CoralieAllioux Aug 29, 2024
a8f0a11
Add data scratchpad controller module
CoralieAllioux Aug 29, 2024
60cbf57
Add dscr controller to filelist
CoralieAllioux Aug 29, 2024
3013a54
Add instruction scratchpad controller
CoralieAllioux Aug 29, 2024
7e7fcc7
Add iscr controller to filelist
CoralieAllioux Aug 29, 2024
cb5d33f
Integrate address decoder in store buffer for scratchpads and create …
CoralieAllioux Aug 30, 2024
16754f5
Merge branch 'scratchpad/store_buffer' into feature/scratchpads
CoralieAllioux Aug 30, 2024
7193e34
Integrate new port list for store_buffer and handle exceptions with n…
CoralieAllioux Aug 30, 2024
195cced
Merge branch 'scratchpad/store_unit' into feature/scratchpads
CoralieAllioux Aug 30, 2024
3553487
Integrate new port list for store_unit and load_unit in load_store_un…
CoralieAllioux Aug 30, 2024
acf2531
Merge branch 'scratchpad/ex_stage' into feature/scratchpads
CoralieAllioux Aug 30, 2024
483caa0
Add needed localparam type for scratchpads and ahb pierphe + integrat…
CoralieAllioux Aug 30, 2024
664917a
Declare needed signals to integrate scratchpads and periph bus
CoralieAllioux Aug 30, 2024
bb52e97
Instantiate ex_stage with additional IOs
CoralieAllioux Aug 30, 2024
9b2c9db
Add address decoder after frontend to support scratchpad targets
CoralieAllioux Aug 30, 2024
71c8fa2
Instantiate dscr and iscr sram and associate controllers; instantiate…
CoralieAllioux Aug 30, 2024
d8b7f5c
Merge branch 'scratchpad/cva6_top' into feature/scratchpads
CoralieAllioux Aug 30, 2024
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6 changes: 6 additions & 0 deletions core/Flist.cva6
Original file line number Diff line number Diff line change
Expand Up @@ -69,6 +69,9 @@ ${CVA6_REPO_DIR}/core/include/wt_cache_pkg.sv
${CVA6_REPO_DIR}/core/include/std_cache_pkg.sv
${CVA6_REPO_DIR}/core/include/instr_tracer_pkg.sv
${CVA6_REPO_DIR}/core/include/build_config_pkg.sv
${CVA6_REPO_DIR}/core/include/ahb_pkg.sv
${CVA6_REPO_DIR}/core/include/address_decoder_pkg.sv
${CVA6_REPO_DIR}/core/include/scratchpad_pkg.sv

//CVXIF
${CVA6_REPO_DIR}/core/include/cvxif_pkg.sv
Expand Down Expand Up @@ -193,4 +196,7 @@ ${CVA6_REPO_DIR}/core/cva6_mmu/cva6_ptw.sv
${CVA6_REPO_DIR}/core/cva6_mmu/cva6_tlb.sv
${CVA6_REPO_DIR}/core/cva6_mmu/cva6_shared_tlb.sv

// Scratchpads
${CVA6_REPO_DIR}/core/address_decoder/address_decoder.sv

// end of manifest
76 changes: 76 additions & 0 deletions core/address_decoder/address_decoder.sv
Original file line number Diff line number Diff line change
@@ -0,0 +1,76 @@
//-----------------------------------------------------------------------------
// Copyright 2024 Robert Bosch GmbH
//
// SPDX-License-Identifier: SHL-0.51
//
// Original Author: Coralie Allioux - Robert Bosch France SAS
//-----------------------------------------------------------------------------

module address_decoder import address_decoder_pkg::*;#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type exception_t = logic,
parameter ADDR_WIDTH = 32
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
module address_decoder import address_decoder_pkg::*;#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type exception_t = logic,
parameter ADDR_WIDTH = 32
module address_decoder
import address_decoder_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type exception_t = logic,
parameter ADDR_WIDTH = 32

) (
input logic clk_i,
input logic rst_ni,
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
input logic clk_i,
input logic rst_ni,
input logic clk_i,
input logic rst_ni,


input logic addr_valid_i, // Input address is valid
input logic [ADDR_WIDTH-1:0] addr_i, // Address to be decoded
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
input logic addr_valid_i, // Input address is valid
input logic [ADDR_WIDTH-1:0] addr_i, // Address to be decoded
input logic addr_valid_i, // Input address is valid
input logic [ADDR_WIDTH-1:0] addr_i, // Address to be decoded


input logic dscr_en_i, // From CSR
input logic iscr_en_i, // From CSR
input logic ahb_periph_en_i, // From CSR

input logic [CVA6Cfg.XLEN-1:0] exception_code_i,

output exception_t ex_o,
output addr_dec_mode_e select_mem_o
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
input logic dscr_en_i, // From CSR
input logic iscr_en_i, // From CSR
input logic ahb_periph_en_i, // From CSR
input logic [CVA6Cfg.XLEN-1:0] exception_code_i,
output exception_t ex_o,
output addr_dec_mode_e select_mem_o
input logic dscr_en_i, // From CSR
input logic iscr_en_i, // From CSR
input logic ahb_periph_en_i, // From CSR
input logic [CVA6Cfg.XLEN-1:0] exception_code_i,
output exception_t ex_o,
output addr_dec_mode_e select_mem_o

);

logic match_any_ahbperiph_region;
logic match_dscr_region;
logic match_iscr_region;
addr_dec_mode_e select_mem_n, select_mem_q;

assign match_dscr_region = config_pkg::is_inside_data_scratchpad(CVA6Cfg, {{64-ADDR_WIDTH{1'b0}}, addr_i});
assign match_iscr_region = config_pkg::is_inside_instruction_scratchpad(CVA6Cfg, {{64-ADDR_WIDTH{1'b0}}, addr_i});
assign match_any_ahbperiph_region = config_pkg::is_inside_ahbperiph_regions(CVA6Cfg, {{64-ADDR_WIDTH{1'b0}}, addr_i});
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
assign match_dscr_region = config_pkg::is_inside_data_scratchpad(CVA6Cfg, {{64-ADDR_WIDTH{1'b0}}, addr_i});
assign match_iscr_region = config_pkg::is_inside_instruction_scratchpad(CVA6Cfg, {{64-ADDR_WIDTH{1'b0}}, addr_i});
assign match_any_ahbperiph_region = config_pkg::is_inside_ahbperiph_regions(CVA6Cfg, {{64-ADDR_WIDTH{1'b0}}, addr_i});
assign match_dscr_region = config_pkg::is_inside_data_scratchpad(
CVA6Cfg, {{64 - ADDR_WIDTH{1'b0}}, addr_i}
);
assign match_iscr_region = config_pkg::is_inside_instruction_scratchpad(
CVA6Cfg, {{64 - ADDR_WIDTH{1'b0}}, addr_i}
);
assign match_any_ahbperiph_region = config_pkg::is_inside_ahbperiph_regions(
CVA6Cfg, {{64 - ADDR_WIDTH{1'b0}}, addr_i}
);


assign select_mem_o = select_mem_n;

always_comb begin : select_mem_p
ex_o = '0;
select_mem_n = select_mem_q;
if (addr_valid_i) begin
unique if (match_dscr_region) begin
// Equal to 0 only if DataScrPresent is set
select_mem_n = DECODER_MODE_DSCR;
if (!dscr_en_i) begin
ex_o = {exception_code_i, CVA6Cfg.XLEN'(addr_i), 1'b1};
end
end else if (match_iscr_region) begin
// Equal to 0 only if InstrScrPresent is set
select_mem_n = DECODER_MODE_ISCR;
if (!iscr_en_i) begin
ex_o = {exception_code_i, CVA6Cfg.XLEN'(addr_i), 1'b1};
end
end else if (match_any_ahbperiph_region) begin
select_mem_n = DECODER_MODE_AHB_PERIPH;
if (!ahb_periph_en_i) begin
ex_o = {exception_code_i, CVA6Cfg.XLEN'(addr_i), 1'b1};
end
end else begin
select_mem_n = DECODER_MODE_CACHE;
end
end
end

always_ff @(posedge clk_i or negedge rst_ni) begin : select_mem_q_p
if (~rst_ni) begin
select_mem_q <= DECODER_MODE_CACHE;
end else begin
select_mem_q <= select_mem_n;
end
end

endmodule
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[verible-verilog-format] reported by reviewdog 🐶

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endmodule
endmodule

23 changes: 23 additions & 0 deletions core/include/address_decoder_pkg.sv
Original file line number Diff line number Diff line change
@@ -0,0 +1,23 @@
//-----------------------------------------------------------------------------
// Copyright 2024 Robert Bosch GmbH
//
// SPDX-License-Identifier: SHL-0.51
//
// Original Author: Coralie Allioux - Robert Bosch France SAS
//-----------------------------------------------------------------------------

package address_decoder_pkg;

// ----------------------
// Address Decoder Mode
// ----------------------

localparam DECODER_MODE_WIDTH = 2;
typedef enum logic [DECODER_MODE_WIDTH-1:0] {
DECODER_MODE_CACHE,
DECODER_MODE_DSCR,
DECODER_MODE_ISCR,
DECODER_MODE_AHB_PERIPH
} addr_dec_mode_e;

endpackage
29 changes: 29 additions & 0 deletions core/include/ahb_pkg.sv
Original file line number Diff line number Diff line change
@@ -0,0 +1,29 @@
//-----------------------------------------------------------------------------
// Copyright 2024 Robert Bosch GmbH
//
// SPDX-License-Identifier: SHL-0.51
//
// Original Author: Coralie Allioux - Robert Bosch France SAS
//-----------------------------------------------------------------------------

package ahb_pkg;

localparam AHBSizeWidth = 3;
localparam AHBTransWidth = 2;
localparam AHBBurstWidth = 3;
localparam AHBProtWidth = 4;

typedef logic [AHBSizeWidth-1:0] size_t;
typedef logic [AHBTransWidth-1:0] trans_t;
typedef logic [AHBBurstWidth-1:0] burst_t;
typedef logic [AHBProtWidth-1:0] prot_t;

// htrans values
typedef enum logic [AHBTransWidth-1:0] {
AHB_TRANS_IDLE,
AHB_TRANS_BUSY,
AHB_TRANS_NONSEQ,
AHB_TRANS_SEQ
} ahb_trans_e;

endpackage
38 changes: 38 additions & 0 deletions core/include/scratchpad_pkg.sv
Original file line number Diff line number Diff line change
@@ -0,0 +1,38 @@
//-----------------------------------------------------------------------------
// Copyright 2024 Robert Bosch GmbH
//
// SPDX-License-Identifier: SHL-0.51
//
// Original Author: Coralie Allioux - Robert Bosch France SAS
//-----------------------------------------------------------------------------

package scratchpad_pkg;

// ----------------------
// Instruction Scratchpad Mode
// ----------------------
typedef enum logic {
ISCR_MODE_FUNCTIONAL,
ISCR_MODE_PRELOAD
} iscr_mode_t;

// ----------------------
// Arbit values
// ----------------------
localparam DSCR_ARBIT_NUM_IN = 3;
localparam ISCR_ARBIT_NUM_IN = 4;

typedef enum logic [$clog2(ISCR_ARBIT_NUM_IN)-1:0] {
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
typedef enum logic [$clog2(ISCR_ARBIT_NUM_IN)-1:0] {
typedef enum logic [$clog2(
ISCR_ARBIT_NUM_IN
)-1:0] {

ISCR_ARBIT_LOAD,
ISCR_ARBIT_STORE,
ISCR_ARBIT_AHB,
ISCR_ARBIT_FRONTEND
} iscr_arbit_e;

typedef enum logic [$clog2(DSCR_ARBIT_NUM_IN)-1:0] {
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
typedef enum logic [$clog2(DSCR_ARBIT_NUM_IN)-1:0] {
typedef enum logic [$clog2(
DSCR_ARBIT_NUM_IN
)-1:0] {

DSCR_ARBIT_LOAD,
DSCR_ARBIT_STORE,
DSCR_ARBIT_AHB
} dscr_arbit_e;

endpackage
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