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$$ directives in board file Verilog are not ignored in code disabled by preprocessor test or /* */
enhancement
New feature or request
#268
opened Apr 13, 2024 by
FPGAEveryday
Enhancement of declaration of bram/brom/simple_dualport_bram/dualport_bram
enhancement
New feature or request
#267
opened Apr 8, 2024 by
rob-ng15
Documentation: possible typo in Silice/learn-silice/Documentation.md?
documentation
Improvements or additions to documentation
#263
opened Jan 17, 2024 by
conversy
inouts cannot be bound using a bit-select syntax
enhancement
New feature or request
#258
opened Dec 30, 2023 by
sylefeb
uart_tx and uart_rx seem to have wrong direction in the Verilog framework file for the ECPIX5-Board
#254
opened Aug 19, 2023 by
at91rm9200
Many boards share a common set of features, yet each board has its own define
discussion
#246
opened Mar 5, 2023 by
sylefeb
Combinational loops may be wrongly detected when passing entire groups as parameters
enhancement
New feature or request
#237
opened Nov 5, 2022 by
sylefeb
Expression trackers in algorithms body lead to confusing (albeit correct) semantics
#235
opened Nov 1, 2022 by
sylefeb
Trackers defined in pipeline stages are not properly tagging variable usage
bug
Something isn't working
#216
opened May 4, 2022 by
sylefeb
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